JPS61170120A - Pulse width expanding circuit - Google Patents

Abstract

PURPOSE:To obtain an output pulse having a constantly expanded pulse width regardless of the quantity of an input pulse width by using an output terminal of a latch circuit as an output terminal as a pulse width expanding circuit, connecting the terminal to an input terminal of a delay circuit and connecting an output terminal of the delay circuit to the 2nd input terminal of the latch circuit. CONSTITUTION:When a negative pulse (8) is incoming to an input terminal 8, the level of an output terminal 9 of the latch circuit 1 changes to logical H. Since the level of the output terminal 11 of the delay circuit remains H for some time, the output of an NAND circuit 4 changes to L level. A signal of an output terminal 9 of the latch circuit 1 enters the input terminal of the delay circuit 12 and the output terminal 11 of the delay circuit changes to logical L via a prescribed delay time. As shown clearly in timing chart in figure, a thin pulse width (8) is expanded into a thick pulse width 9. the pulse width 9 is set only at a delay time of the delay circuit and independent of the input pulse width.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that extends the width of an IC pulse using a pulse input as a trigger to generate a necessary typing signal, a so-called pulse stretcher circuit.

[Conventional technology]

A typical example of a conventional pulse width expansion circuit is shown in FIG. In FIG. 6, a negative pulse signal input to the input terminal 103 is input to the first gate of the NAND circuit 101, and the output terminal 104 is immediately set to a high potential (hereinafter abbreviated as H), while at the same time there is a delay formed by an inverter. After a certain delay time through the circuit 102, it is input to the second gate of the NAND circuit 101 and the output terminal 104 is set to H. At this time, the output terminal 104 is connected to the first gate and the second gate is at a low potential (
The pulse width of the pulse signal input to the input terminal 106 is outputted to the output terminal 104 as a signal whose pulse width has been expanded by the delay time of the delay circuit 102.

[Problem that the invention seeks to solve]

However, in the conventional pulse width expansion circuit described above, if the manually generated pulse width is shorter than the delay time of the delay circuit, no pulse is output to the output terminal of the delay circuit, and the purpose of expanding the pulse width cannot be achieved. do not have. Also, input pulse 1
Even if the delay time is longer than the delay time of the delay direction path, the output pulse width of the delay circuit will become shorter as it approaches, or the output as a 5k circuit will increase the pulse width due to the size of the human pulse width. There was a problem of unstable operation because the pulse width changed. Therefore, the present invention is intended to solve the above problems in the conventional circuit, and its purpose is to obtain a constant output pulse width regardless of the input pulse width, and to achieve stable operation. To provide a pulse width expansion circuit.

[Steps to solve problems]

It consists of a latch circuit that detects and stores when a pulse is input, and a delay circuit that obtains a delay time corresponding to one prefecture (to extend a thin input pulse), and the first input terminal of the latch circuit is The output terminal of the latch circuit is an output terminal of the pulse width expansion circuit of the present invention and is also connected to the input terminal of the delay circuit. It is characterized in that it is connected to the second input terminal of the latch circuit.

[Effect]

According to the above configuration of the present invention, the input state of the manually input pulse is stored by the latch circuit. Then, the latched state signal enters the delay circuit, and the i!
! ! After an extended period of time, the latch state of the latch circuit is released. Therefore, as long as the input pulse width is shorter than the delay time of the delay circuit, 1. A human pulse with an arbitrary pulse width, even if it is different or thicker, is converted into an output signal with a pulse width equal to the delay time of the same delay circuit.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, the internal circuit surrounded by a broken line 1 is a latch circuit, and the internal circuit surrounded by a broken line 2 constitutes an introductory circuit. Inside the broken line 1, the output terminal of the NAND circuit 3 is connected to the first human power gate of the NAND1 path 4, and the output terminal of the NAND circuit 4 is connected to the NAND1 path 5
The latch circuit 1 is configured by the NAND circuit 6 and the NAND circuit 4. Also, the latch circuit 41 is NAND! No. 1 of Langro 6
It has an input terminal 8 connected to the human power gate and a reset terminal connected to the second human power gate of the NAND circuit 4).

+IJ delayed recirculation 2-digit inverter 5. , S, and 7 are connected in series, and the slow decay time is changed by adjusting the inverter's power and power. The output 3 of the NAND circuit 5 is the output of the latch circuit j, which is the output of the latch circuit j, and is the output of the 111th delay circuit 2.
It is connected to the input gate of the inverter 5, which is the 0 input. The output terminal of the inverter 7, which is connected to the output terminal 11 of the delay circuit 2, is connected to the second manual gate of the NAND circuit 4, which is the reset terminal of the latch circuit 1. Further, the output terminal of the @8C latch circuit 1 also serves as the 14i force switch 9 of the circuit of the present invention. Next, the operation of the above circuit will be explained. FIG. 2 shows a timing chart representing the operation of the circuit of FIG. 1. In Figure 2, the left elevation j of each waveform
The numbers shown in Figure 1 correspond to the numbers at each point in the circuit in Figure 1, and the timing chart in Figure 2 represents the operating waveforms at the corresponding points. Now, in the circuit shown in Figure 1, at the beginning (8), Hl (9), and (10') are ■(
, (11) is H.

Next, when a negative pulse signal (8) comes to the input terminal 8, the output terminal 9 of the latch circuit 1 changes to H. In this case, the output terminal 11 of the delay circuit (the output terminal stays at H for a while, so the NA
The output id of the ND circuit 4 changes to L.

Therefore, even if the pulse at the input terminal 8 ends and the state becomes H, the output terminal 9 n of the latch circuit remains at H. Now, the signal at the output terminal 9 of the latch circuit 1 enters the input terminal of the delay circuit 12, and after a certain delay time, the output terminal 11 of the delay circuit changes to L. When the output signal of this delay circuit changes to L, the output terminal of the NAN'D circuit 4 becomes H, the latched state is released, and the output terminal of the latch circuit 1 returns to L.

The above operation is shown in the typing chart in Figure @2.

However, here, the input pulse width is assumed to be shorter than the delay time of the delay circuit. Note that if the manual pulse width is wider than the delay time of the delay circuit, there is no need to extend the pulse width by -6 = originally. Now, f. If you look at the timing chart in Figure 2, you will see that the narrow pulse width shown by curve (8) has been expanded to the thick pulse width shown by (9). Here, the pulse width in (9) can be set only by the delay time of 11ffJ m and does not depend on the input pulse width. Furthermore (10
) signal td is an inverted signal of (9), and as a peak signal of the pulse width expansion circuit of the present invention, both (9) and (10
), but you can use either one. In other words, the output terminal 10 of the NAND circuit 4 can also be used as the output terminal of the circuit of the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. The circuit of FIG. 3 differs from the circuit of FIG. 1 only in the specific configuration of the delay circuit, and since the other configurations are the same, the delay circuit will mainly be described. Delay circuit 5 in the circuit of FIG.
2 are cascade-connected inverters 55-. 36,57.5
The input terminal of the delay circuit is connected to the gate of the 9-digit inverter 55 and the first gate of the NAND circuit @59, and the second gate of the NAND circuit 39 is connected to the output terminal of the inverter 68. Further, the output of the NAND circuit 59 serves as an output terminal of the delay circuit 32.

Characteristics of the delay circuit 62 (for dH input signal, N
It operates according to the slower change of gate 59 of the ANDM path 59 and the second gate, and changes faster for the human input signal of L, so the time of section L in (11) in Fig. 2 is short. It becomes like this. In other words, this is an example of a circuit that has been improved so that it can quickly prepare for receiving the next input pulse.

FIG. 4 is a circuit diagram showing a fifth embodiment of the present invention. The circuit of FIG. 4 differs from the circuit of FIG. 1 only in the specific structure of the latch circuit, and since they have the same structure, the latch circuit will mainly be explained.

The latch circuit 41 in FIG. 4 has a circuit configuration in which the NAN I) circuit in the latch circuit 1 in FIG. 1 is replaced with a NOR circuit. Therefore, FIG. 4 shows a circuit that operates in response to positive polarity pulses.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention. In the 5th M, the latch circuit 51 is a NAND circuit 56, NA
It is composed of an ND circuit [54] and an inverter 55. In the latch circuit 51, the NAND circuit 53 and the NAND
The connection relationship of the D circuit 54 is the same as that of the NAND circuit 6 and the NAND circuit 4 of the latch circuit 1 of the circuit shown in FIG. However, the inverter 55 is added to the latch circuit glue + "4 children 11, and the NAN
The output of the inverter 55 is connected to the 54th port of the Dl path 54. Further, the delay circuit 52 is composed of a CR delay circuit including a resistor 56 and a capacitor 57.

The relationship between the latch circuit 51 and the delay circuit 52 is the same as that between the latch circuit and the delay circuit in FIG. The characteristics of the circuit shown in FIG. 5 indicate that the delay circuit may be constructed from a basic resistor R and capacitor C.

As can be seen from the above embodiments, a specific circuit example of a latch circuit or a delay circuit can be obtained as long as the essential configuration of the latch circuit and delay circuit of the present invention is such that the latch circuit is reset by the output signal of the delay circuit. It can be seen that various other configurations are possible.

〔Effect of the invention〕

As mentioned above, according to the present invention, the functions are divided into a latch circuit that detects and stores the arrival of an input pulse, and a delay circuit that has a delay time corresponding to the pulse width that you want to extend, so the manual pulse width The effect is that an output pulse with a constant extended pulse width can be obtained regardless of the magnitude of the pulse width. Further, for the same reason as mentioned above, the operation does not become unstable depending on the magnitude of the input pulse, and as a result, a circuit that is stable against changes in voltage, temperature, etc. can be obtained.

In addition, regardless of the manual pulse width, if you set a delay time corresponding to the pulse width you want to extend to the car using the delay circuit, you can obtain the desired pulse width extension circuit, providing a circuit that is easy to design and has a high degree of freedom. It also has the effect of

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the first embodiment of the present invention, Fig. 2 is a timing chart showing the operation of the circuit in Fig. 1, and Figs. Second and fifth inventions,
11EJ road diagram showing the fourth embodiment, and FIG. 6 shows an example of the conventional circuit. 1 route map・1.31,41.51・
... Latch circuit 2, 52, 42.52 ... Delay circuit 6.4, 59, 55.54 ... NAND circuit 5, 6. 7. 55. 56. 57. 58.
55...Inverter circuit 45.44...NOR circuit 56...Resistor 57...Capacitor 8...Input terminal 9 of the circuit of the present invention... Output terminal of the circuit of the invention. that's all

Claims (1)

[Claims] It consists of a latch circuit that detects and stores the input of a pulse, and a delay circuit that obtains a delay time corresponding to the pulse width to which a thin input pulse is desired to be expanded.
The input terminal is an input terminal into which a pulse signal is input, and the output terminal of the latch circuit is an output terminal of the pulse width expansion circuit of the present invention and is also connected to the input terminal of the delay circuit. A pulse width expansion circuit characterized in that an output terminal of the delay circuit is connected to a second input terminal of the latch circuit.