JPS60100820A - Monostable multivibrator - Google Patents

Abstract

PURPOSE:To attain a clearing action through a monostable multivibrator by applying an input signal to a clock terminal of a D type FF and providing a delay circuit between a reset terminal and an output terminal of said FF. CONSTITUTION:A D type FF7 is provided together with a delay circuit 8 and an AND gate 9. The circuit 8 consists of inverters 10 and 11, resistances 12 and 14, a capacitor 13, etc. When an input signal IN is changed to a high level from a low level, the output Q' of the FF7 is changed to a low level from a high level. Therefore the potential of a node N3, i.e., the output of the inverter 10 rises up gradually by a time constant of the capacitor 13 and the resistance 12, respectively. When the potential of the N3 reaches the threshold value of the inverter 11, the output of the inverter 11 is inverted to a low level from a high level. As a result, the potential of a reset terminal R of the FF7 is set at a low level. Then the output Q' is changed to a high level from a low level, and the non- reverse output Q is changed to a high level from a low level. The output Q is used as an output OUT to obtain an output of a desired pulse width.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a monostable multivibrator KlaL, and particularly to a monostable multivibrator KlaL that is constructed of basic gate circuits and the like and is capable of clearing operation.

(Technical background) As a monostable multibibreak, generally.

It is constructed by using an integrated circuit device such as the 74L8123 type and externally attaching a resistor and a capacitor. However, since such an integrated circuit device is basically constructed using elements such as transistors, it is impossible to use it in a gate array LSI device. In order to use it in a gate array LSI device or the like, it is necessary to construct a monostable multi-by-break using basic gates such as seven lip-flops and an AND gate.

(Prior Art and Problems) FIG. 1 shows a monostable multivibrator constructed using conventional basic gates. The circuit shown in the figure includes a Nandt gate 11, inverters 2, 3, 4, a resistor 5, and a capacitor 6.

The operation of the circuit shown in FIG. 1 will be explained with reference to FIG. When the input signal IN changes from a low level to a high level, the potential at the output point of the inverter 3, that is, the node N1 rises from a low level to a high level after a delay time TO corresponding to a time constant determined by a resistor 5 and a capacitor 6. Therefore, the output of the inverter 4, that is, the potential of the node N2 also decreases from a high level to a low level almost simultaneously, and the output OUT of the Nant gate 1 rises from a low level to a high level.

Therefore, the output signal OUT outputs a signal with a time width T from the 9th point in time when the input signal IN rises. When the input signal IN falls from a high level to a low level, the charge in the capacitor 6 is rapidly discharged by the internal transistor of the inverter 3, and the potential at the node N1 quickly falls from a high level to a low level. As a result, the potential of the node N2 also changes from a low level to a high level. At the falling edge of the input signal IN, the input signals of the Nant gate 1 do not go high at the same time, so the output signal OUT remains at the high level.

However, in the circuit of FIG. 1, if the width of the human input pulse IN is shorter than the output signal width T, as shown by the broken line in FIG. 2, the output pulse OUT will be shorter than the predetermined time width T. This has the disadvantage that it does not operate as a monostable multivibrator. Furthermore, the circuit shown in FIG. 1 has the disadvantage that it is not possible to perform a so-called clear operation in which the output of the output signal OUT is stopped as necessary during the output of the output signal OUT.

(Object of the invention) The object of the present invention is to solve the problems of the conventional type described above.
Based on the concept of using a D-type flip-flop and a delay circuit in a monostable multivibrator mainly constructed using basic gates, it is possible to stabilize an output pulse with a sufficiently long time width without being affected by the pulse width of the input signal. The purpose of the present invention is to enable clearing operations to be performed at any timing as needed.

(Structure of the Invention) According to the present invention, the object is to provide a monostable multi-channel multi-channel flip-flop with a delay circuit inserted between the output terminal and the reset or preset terminal of the D-type flip-flop and the flip-flop. This is accomplished by providing a vibrator.

(Example of the invention) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows the configuration of a monostable multivibrator according to an embodiment of the present invention. The circuit shown in the figure includes a D-type flip-flop 7, a delay circuit 8, and an AND gate 9. Delay circuit 8 includes two inverters lO and 11. It is composed of resistors 12, 14, capacitor 13, and the like. Note that the inverter IO is of a so-called open collector type. The data input terminal of the D-type flip 70 tube 7 is connected to a power supply Vcc, etc., and a high-level input signal is always applied thereto.

The operation of the circuit shown in FIG. 3 will be explained with reference to FIG. Fourth
Figure (a) shows that when the clear signal CLR is always at a high level,
That is, it shows the operation waveforms of each part when no clearing operation is performed. In this case, when the input signal IN changes from a low level to a high level, the inverted output page of the D-type flip-flop 7 changes from a high level to a low level. Therefore, the output of inverter 10, that is, the potential of node N3 gradually increases toward power supply Vcc with a time constant determined by resistor 12 and capacitor 13. When the potential of node N3 reaches the threshold voltage of inverter 11, the output of inverter 11 is inverted from high level to low level. As a result, the potential of the node N4, that is, the reset terminal R of the D-type 7-lip 70 tube 7 becomes low level.
The knob 7 is reset. Therefore, the inverted output page changes from low level to high level, and the non-inverted output Q changes from high level to low level. By taking out this non-inverted output Qf as the output signal OUT, an output with a desired pulse width T can be obtained. In the circuit shown in FIG. 3, the output Q of the D-type 7-rig flop 7 is the input signal I.
Changes from low level to high level when N rises,
After that, the signal at the reset terminal R remains at a high level until it becomes a low level, so it operates normally even if the pulse width of the input signal IN is narrower than the pulse width T of the output signal OUT. The circuit is triggered on the rising edge of the input signal IN.

FIG. 4(b) shows waveforms of various parts when a clearing operation is performed. As shown in the figure, the initial clear signal CLR
When input signal IN rises from a low level to a high level while N is at a high level, the potential of node N3 gradually increases according to a time constant determined by resistor 12 and capacitor 13. Then, the potential of the node N3 changes to the inverter 11.
If the clear signal CLR goes low before reaching the threshold voltage of , the D-type flip-flop is immediately reset and the inverted output page changes from low to high.

As a result, the output of the inverter 1o, ie, the potential of the node N3, is rapidly lowered to a low level. Therefore, even if the clear signal CLR becomes high level again after that, the inverted output page remains high level, and the output signal OUT
is maintained at a low level. That is, in the circuit shown in FIG. 3, the clearing operation is performed when the clearing signal CLR falls at a shedge.

In the circuit shown in FIG. 3, the resistor 14 is connected to the inverter 1.
This is a protective resistor that prevents a large current from flowing from the capacitor 13 to the output transistor inside the inverter 1O when the output of 0 changes to a low level, thereby preventing destruction of the transistor.

FIG. 5 schematically shows a monostable multivibrator according to another embodiment of the invention. The circuit shown in the figure includes a D-type flip 70 tube 15 and a delay circuit 16. In this circuit, the data input terminal of the D-type flip-flop 15 is connected to ground and is always at a low level. and.

The non-inverted output Q of the D-type flip-flop 15 is input to the delay circuit 16 , and the output of the delay circuit 16 is connected to a preset terminal of the D-type flip-flop 15 . In addition,
If a clear operation is required, the output of the delay circuit 16 and the clear signal may be input to a full AND gate, and the output of the AND gate may be input to the preset terminal DL. Further, as the delay circuit 16, a circuit similar to the delay circuit 8 of FIG. 3 is used.

The operation of the circuit in FIG. 5 can be considered similar to the operation of the circuit in FIG. 3, so a detailed explanation will be omitted. FIG. The internal structure of a type flip-flop is shown. That is, Fig. 6(b
) The D-type flip-flop shown in block circuit form has the configuration shown in FIG. 6(a) and consists of six NAND games).
17,18. ..., 22. Since the circuit operation of such a dope type flip-flop is well known, a detailed explanation thereof will be omitted.

(Effects of the Invention) - As described above, according to the present invention, it is possible to configure a monostable multivibrator based on basic gate circuits such as flip 70 tubes, AND gates, and inverters. Suitable for LSI etc.

Furthermore, since it operates at the rising edge of the input signal, the input pulse width only needs to be at least the minimum clock width, and can be made extremely small compared to the conventional type. This also applies to the clear operation, and the clear operation can be performed accurately at the edge of the clear signal. Further, even when the time constant of the delay circuit is increased to lengthen the output pulse width, the device operates stably without causing chattering of the output signal.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing a conventional monostable multivibrator, Fig. 2 is a waveform diagram showing the operation of the circuit in Fig. 1, and Fig. 3 is a monostable multivibrator according to an embodiment of the present invention. The block circuit diagram shown in FIG. 4(a) and (
b) is a waveform diagram showing the operation of the circuit of FIG. 3, FIG. 5 is a schematic block diagram showing a monostable multi-bi break according to another embodiment of the present invention, and FIGS.
) is a block circuit diagram showing the configuration of a D-type flip-flop. ..., 22... Nant Gate, 2゜3.4, 10.11... Inverter, 5,
12.14...Resistor 16, 13...Capacitor, 7
．． 15...D-type flip-flop, 8.16...Delay circuit, 9...AND gate. Patent applicant Fujitsu Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi Figure 1 Figure 2 Figure 4 (.) Figure 4 (b) Hi Figure 6(a)

Claims (1)

[Claims] A D-type flip-flop whose data input terminal is kept at a constant potential and an input signal is input to its clock terminal, and a delay circuit inserted between the output terminal of the D-type flip-flop and a reset or preset terminal. Stable multi-vibration 0