JPS5834052B2 - flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit capable of operating at small signal levels such as TTL and CML.

Flip-flop circuits have two stable states and can hold either one of them indefinitely, but if there is an external excitation, the flip-flop circuit can suddenly switch from the previously held stable state to the other stable state. Changes to

In this case, in the current transistor flip-flop, in order to invert from one stable state to the other stable state with a power supply voltage of about IOV, it is necessary to apply a large signal of about IOV from the outside.

On the other hand, the output voltage of the TTL gate circuit is 3.5V at the "1" level and 0.5V at the "0" level. l5V, the output voltage of the OML gate circuit is 10, SV at the "1" level.

°“On level -1,6■, both of which are extremely small.

Therefore, for signals such as TTL and OML, flip
It is not possible to flip the flop.

FIG. 1 shows a typical configuration example of a conventional flip-flop circuit.

In the figure, the main transistor Q3 is now off,
Assuming that Q4 is on, in order to reverse this state, input S1 of input transistor QA is set to H (high level).
When the input S2 of the input transistor QB is set to L (low level), the transistor QA is turned on and the transistor QB is turned off, and the connection point N2 attempts to change from L to H. is input, the point N2 does not easily become H, and in order to make it H, transistor QA must flow a sufficiently large current (f).

The main transistor Q3 is on and Q4 is off, and to reverse this state, the input S1 of the input transistor QA
The same applies when setting the input transistor QB to L and the input S2 of the input transistor QB to H.

Therefore, in order to cause state reversal in the flip-flop circuit shown in FIG. A signal as large as IOV is required, and it has not been possible to invert it using signals such as TTL and OML.

The present invention aims to eliminate the above-mentioned drawbacks by using TTL.

The purpose of this invention is to realize a flip-flop circuit that can invert even a small signal such as OML.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a connection diagram of the flip-flop circuit, and FIG. 3 is an operation time chart in FIG. 2.

Initially, the level of input S1 is H (high level), the level of input S2 is L (low level), and transistor Q
9 is on and Q10 is off, each level of the flip-flop is as shown in period 1 in FIG.
N2 is high, N3 is high.

N4 is L, N5 is H, and N6 is L.

Next, when the input S1 changes from H to L and the input S2 changes from L to H, the transistor Q9 turns off and the transistor Q10 turns on, as shown in period 2 in FIG.

When transistor Q10 turns on, N5 changes from H to L, and transistor Q8 turns off.

At this time, since N6 is at L, transistor Q6 is off.

Therefore, since transistors Q8 and Q6 are off,
N2 is charged up by transistor Q2,
It suddenly becomes H.

In this case, even if N2 becomes H, N6 is a large resistance R4
Since the charge-up is determined by the time constant of the gate capacitance of the transistor Q6 and the gate capacitance of the transistor Q6, the transistor Q6 does not turn on immediately.

On the other hand, when N2 becomes H, transistor Q3 turns on.

Also, when N1 is H, N3 is charged up through resistor R1 and becomes H, and transistor Q5 is on, so N1 becomes H as a result of being charged up through resistor R1. It is discharged through Q5, and N1 becomes L.

Even if N1 becomes L, the level of N3 remains H due to the operation of resistor R1.

Further, even if N2 becomes H, N4 is not immediately charged up because of the resistor R2, and N4 maintains L.

As described above, input S1 changes from H to L, and input S2 changes from L to H.
In the state immediately after N1 changes from H to L and N2 changes from L to H, N1 goes up, N2 goes up, N3 goes up, N4 goes up, N5 goes up, and N6 goes up.

At this time, transistors Q3 and Q5 are turned on, setting N1 to the L level, and transistor Q7 is turned off.

On the other hand, with respect to N2, transistors QB and Q4 are turned off, setting N2 to an H level, and at this time, transistor Q6 is turned off.

Next, after a certain amount of time has passed after N1 is determined to be L and N2 is determined to be H, resistors R1 to R4 and transistor Q5
The level changes depending on the time constant due to the capacitance of ~Q8, and the state shown in period 3 in FIG. 3 is reached.

That is, N3 is discharged through the resistor R1 and becomes L, and the transistor Q5 is turned off.However, N4 is charged up from N2 through the resistor R2, and the transistor Q7 is turned on, so even if the transistor Q5 is turned off, N1 is turned off. Maintain L level.

On the other hand, N6 was at L level immediately after N2 became H, but is charged up from N2 through resistor R4 and becomes H level.

This turns on transistor Q6, but since Q4 is off even though Q6 is on, N2 maintains the H level.

Next, when the input S1 goes from L to H and the input 82 goes from H to L, as shown in period 4 in Figure 3, the transistor Q9 turns on, so N4 goes up, N2 goes up, and N1 goes up. However, even when N1 becomes H, N5 is not immediately charged up due to resistor R3 and remains at L.

When the time constant determined by the capacitances of the resistors R1 to R4 and the transistors Q5 to Q8 has elapsed, the state shown in period 1 in FIG. 3 is reached.

As described above, the flip-flop circuit operates while repeating steps 1 to 4 in FIG. 3.

In addition, in the above operation, the transistor Q9 and the resistor R2
The circuit consisting of the transistor Q10 and the resistor R3 amplifies the human power S1 and S2 to some extent, respectively, and the circuit consists of the transistor Q7. The input to Q8 serves to facilitate the inversion of the flip-flop circuit.

Thus, according to the present invention, six transistors Q5, Q6, Q7゜Q8 are added to the conventional flip-flop.
, Q9 , Ql 0 and four high resistances R1°R2
, R3, and R4, the stable state of the flip-flop can be reliably reversed with a small signal, so TTL and OML levels can be used as they are.

[Brief Description of the Drawings] Fig. 1 is a diagram showing a configuration example of a conventional flip-flop circuit, Fig. 2 is a connection diagram of a flip-flop circuit showing an embodiment of the present invention, and Fig. 3 is a diagram showing a configuration example of a conventional flip-flop circuit. It is an operation time chart in the figure. QA, QB: input transistor, Q3. Q4: Main transistor, Ql, Q2: 1 helang resistor for diode, Q
5. Q6: Second transistor, Q? . Q8: third transistor, Q9, Ql 0: input side transistor, R1-R4: high resistance, 81, 82: input signal, vDD, ■ss: connection power supply.

Claims (1)

[Claims] 1 In a flip-flop circuit in which the outputs N1 and N2 of main transistors Q3 and Q4 are directly coupled to the inputs of the other main transistor, second transistors Q5 and Q6 are connected in series with each main transistor, and the main transistor The output of the other main transistor is inputted through the first high resistance R1, R4, and the output of the other main transistor is inputted to the second high resistance R4 in order to maintain the output potential of the main transistor.
, 2, the third transistor Q7.
The input signal S1.QB is provided separately and input to the flip-flop circuit. A flip-flop circuit characterized in that the outputs of input transistors Q9 and Q10 to which S2 is applied are input to the third transistor.