JPS59214305A - Complementary mos type oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and to facilitate oscillation by inserting a current limiting resistance between a CMOS inverter and a power source, and connecting an MOS transistor (TR) which is turned on only for a specific period when the oscillation is started in parallel to said resistance. CONSTITUTION:A P channel MOSTR19 is connected to one current limiting resistance 17 in parallel and an N channel MOSTR20 is connected to the other current limiting resistance 18 in parallel; and control signals S2 and S1 which go up to a level ''0'' and down to a level ''1'' for the specific period in the start of oscillation are supplied to the gates of both MOSTRs 19 and 20. Thus, the MOSTRs 19 and 20 are turned on only in the start of oscillation to flow a large current to a CMOS inverer 13, and consequently the starting of oscillation is facilitate and a current is flowed through the current limiting resistances 17 and 18 in an oscillation state afer the start of oscillation to wave electric power.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS type oscillator circuit using a CMOS inno-Z-type.

[Technical background of the invention]

Figure 1 shows a conventional CMOS designed to reduce power consumption.
! FIG. 2 is a circuit diagram showing the configuration of a (complementary MOS type) oscillation circuit. This oscillation circuit has a P-channel MOS to 7 transistors l1 between the positive power supply voltage application point and the reference power supply voltage vs8 (earth voltage) D application point.
A CIViOS inverter I3 is constructed by inserting an N-channel MOS transistor l2 in series and connecting the darts of both MOS inverters 11 and 12, and a feedback resistor I4 is connected between the input and output terminals of this CMOS inverter l3. An oscillation feedback circuit I6 consisting of a crystal resonator 15 and a crystal resonator 15
Moreover, in order to reduce power consumption, a current limiting resistor is installed between the P-channel MOS transistor Zl and the DD application point and between the N-channel MOS transistor IZ and the V88 application point. 17.1
8 each can be inserted. The values of the current limiting resistors 17 and 18 are determined by the power consumption and various conditions of the oscillation circuit.

[Problems with background technology]

In the oscillation circuit shown in FIG. 1, if the value of the current limiting resistor 17.18 is increased, the CMOS inverter 1
3 each MO8 transistor IZ.

The current flowing through 12 is reduced, thereby reducing power consumption. However, the resistance 17.
If the value of 18 is too large, the disadvantage is that it takes a long time to change from the oscillation stop state to the oscillation state, and oscillation cannot be easily started.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a complementary MOS type oscillation circuit that consumes less power and can easily oscillate.

[Summary of the invention]

According to this invention, a current limiting resistor is inserted between the CMOS inverter and the power supply, and a complementary MOS transistor is connected in parallel with the resistor, the conduction of which is controlled only during a predetermined period when oscillation starts. type oscillator circuit is provided.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a configuration according to an embodiment of the present invention, and the same reference numerals are used for parts corresponding to those in FIG. 1, and the explanation thereof will be omitted. In this embodiment circuit, a P channel MOS transistor 19 is connected in parallel to the one current limiting resistor 17, and an N transistor is connected to the other current limiting resistor 18.
Channel MOS) transistors 2o are connected in parallel, and the dirt of both MO8) transistors 19 and 20 is set to It o1p level and 4% 1 for a predetermined period when oscillation starts.
Control signal S2.17 level. It is designed to supply Sl. The value of the conduction resistance when both MO8) transistors 19 and 2θ are conductive is set to be smaller than at least the value of the current limiting resistor 17, 18.

In such a configuration, when oscillating, the gate of the P-channel MOS transistor 19 has 110 I
The control signal s2 set to I level is the N-channel MO
A control signal Sl set to the '1# level is input to the dart of the S transistor 2o, and both MO
Both 8+- transistors 1920 are rendered conductive.

At this time, the conduction resistance values of both MO8 transistors 19 and 20 are set to be sufficiently small, so that a sufficiently large current can flow through the CMOS inverter 13. Therefore, oscillation can be easily caused.

On the other hand, after oscillation has started, the P channel MOS transistor I, which has been set at the II OIj level,
The control signal S2 inputted to the gate 9 is inverted to the level 1", and the control signal S2 inputted to the gate 20 of the pN channel rvIOs transistor 20 is similarly set to the level 1" up to the level 1. Sl is inverted to the ``'0'' level. As a result, both MOS transistors 19.
20 are both cut off. In this cut-off state, the value of the cut-off resistance of both MO8 transistors 19 and 20 is extremely large. Therefore, in this case CMOS inverter Z, ? A current flows through the current limiting resistors 17 and 18, and the value of this current can be made sufficiently small due to the presence of the current limiting resistors 17 and 18. Further, since oscillation has already started, there is no problem caused by passing a small current through the CMOS inverter 13.

In this way, in the above embodiment circuit, the MO is activated only at the start of oscillation.
S) CMOS with transistors 19 and 20 in conductive state
A large current is passed through the inverter 13, thereby facilitating the start of oscillation, and furthermore, when the oscillation is in the oscillation state after the start of oscillation, current is passed through the current limiting resistors 17 and 18, thereby reducing power consumption. This is what I did.

Therefore, in a system using the above embodiment circuit, stable circuit operation can be obtained in a short time after power is turned on. Furthermore, when testing a system that employs the oscillation circuit of the above embodiment, the oscillation circuit itself becomes stable in a short period of time, so the test time can be shortened and the cost required for testing can also be reduced. be.

FIG. 3 shows a specific example of a control circuit for generating the control signals S1 and S2 supplied to the transistors 19 and 20 of the MO8) transistors. This circuit is '0' after power on.
``Level @l 1 level b■'' A circuit that generates a control signal S1゜S2 that is inverted to ``1'' level and ``0# level after counting 8 times the oscillation pulse obtained at the output terminal of the CMOS inverter I3. It is. This circuit connects three D-type flip-flops 31 to 33 in cascade so that the output of the previous stage is used as the clock (CK) input of the latter stage, and the data (D) input of the first and second stage flip-flops 31 and 32. The output signal is supplied to the terminal to form a pinary counter of 1 bit each, and the data (
D) The input terminal is connected to the VDD application point to input "'1# level data," and the clock (CK) input terminal of the first stage flip-flop 3Z is supplied with the clock (CK) generated by the CMOS inverter 13 via the inverter 34. A power supply reset circuit 37 is provided, which inputs an oscillation signal of 9 pulses, and connects a resistor 35 and a capacitor 36 in series to generate a reset signal that is at the on level immediately after the stain source is turned on. Each of the above 7 lip-flops 31
~33 reset) (R) is configured to be input to the input terminal, and one control signal Sl is input to the final stage flip-flop 33.
The other control signal S2 is obtained by inverting this output enable with an inverter 38.

In the control circuit having such a configuration, the capacitor 36 is sufficiently charged immediately after the power is turned on.
Since the terminal voltage has not reached ■DD, each flip-flop 31 to 33 is reset and each output Q
is set to 1" level. Therefore, one control signal S, is at It 17 level, and the other control signal S2 is (
t OII level. Here, one control signal S is applied to the dart of the N-channel MOS transistor 20 in the circuit shown in FIG.
2 are similarly input to the gates of the P-channel MO8 transistor 19, so at this time both MO8 transistors 19 and 20 are rendered conductive as described above.

After the power is turned on, the oscillation circuit shown in Figure 2 operates and the C
Oscillation pulses are sequentially output from the MOS inverter 13,
This pulse is input as a clock to the first stage flip-flop 31 via the inverter 34 in the circuit of FIG. By this time, the capacitor 36 has been charged with the vDD battery and the reset state of the horns 31 to 33 of each flip-flop 70 has been released, so each of the flip-flops 31 to 33 has been released from the reset state.
33 performs a counting operation in synchronization with the clock input. Since the I II level is always input as input data to the final stage 7 flip-flop 33, after the input from the oscillation circuit eight times to the first stage flip flop 31, the final stage 7 Ripfrotsuzo 33 output possible is pa 0
``After being reversed to the level, it does not change as it is.

That is, after the pulses are counted eight times by the three flip-flops 31 to 33, one control signal S1 becomes (10
1 level, and the other control signal S2 is set to '1' level, so at this time, as described above, both MO
8 transistors 19, 20 are both turned off.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, instead of the current limiting resistor 17.18, it is also possible to use a MOS transistor having a predetermined resistance.

Furthermore, in the control circuit shown in FIG. 3, we have explained the case where the level of the control signal S I H82 is inverted after counting the oscillation pulses of the oscillation circuit eight times. It is also possible to change the number of ruses.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a complementary MOS type oscillation circuit that consumes less power and can easily oscillate.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional CMCJS type oscillation circuit, and Figure 2 is a circuit diagram of a conventional CMCJS type oscillation circuit.
The figure is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a circuit for generating signals used in the circuit of FIG. 13...CMOS inverter, 16...Oscillation feedback circuit, 17.18...Current limiting resistor, 19.20...
・MOS) transistor.

Claims (4)

[Claims] (1) Two MOs with different conductivity types between a pair of power supplies
S) A complementary MO8 type inverting circuit formed by inserting transistors in series, an oscillation feedback circuit connected between the input and output terminals of this inverting circuit, and a current limiting resistor inserted between the above inverting circuit and the power supply. , and a switch element connected in parallel to the current limiting resistor. (2) The complementary MO3 type oscillation circuit according to claim 1, wherein the switch element is controlled to be conductive only for a predetermined period at the time of starting oscillation. (3) The complementary MO8 type oscillator circuit according to claim 1, wherein the switching element is constituted by a MOS transistor, and the value of the resistance when conducting is set to be smaller than at least the current limiting resistor. . (4) The switching element is set to one level before the start of oscillation, and is turned on based on a control signal that is set to the other level after the oscillation/zerus generated by the inverting circuit reaches a predetermined number of times after the start of oscillation. A complementary MO8 type oscillator circuit according to claim 1, which is controlled.