JPS63269822A - Phase detection circuit - Google Patents

Abstract

PURPOSE:To obtain a phase detecting characteristic without having a blind sector and with superior linearity, by providing a delay circuit to be connected to the common reset terminal of two signal detection circuits in a reset circuit which generates a reset signal. CONSTITUTION:When an input signal R1 is set at an L level, a sigmal is detected by setting both outputs of NAND gates 1 and 3 at H levels. Also, when an input signal V1, changes from the H level to the L level, the signal is detected by setting both outputs of NAND gates 6 and 7 at the H levels. Thus, since the both outputs of the NAND gates 1 and 3, and 6 and 7 go to the H levels by the arrival of two signals with the L levels, the output of the NAND gate 9 of the reset circuit 13 changes to the L level, and it is inputted to the delay circuit 10. And a reset operation can be performed by delaying it at the circuit 10 and adding it on the NAND gates 4 and 5 via the common reset terminal A of the signal detection circuits 11 and 12. In such a way, it is possible to obtain the phase detecting characteristic without having the blind sector and with the superior linearity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase detection circuit that detects a phase difference between two signals used for PLL control.

(Prior Art) Conventionally, this type of circuit is composed of two signal detection circuits 16 and 17 and a reset circuit 18 as shown in FIG. 5, and detects the arrival of two signals>3 R5 and vl. The detected reset signal (output signal of NAND gate 9) is gate-synthesized (added to NAND gates 2 and 8) with the two signal arrival detection outputs, respectively, and phase detection outputs U, D, are output.

(Problem to be Solved by the Invention) However, in such a configuration, the detection signal appears only in the output of the side where the signal arrived first, and if the signals arrive at the same time, the detection signal does not appear in either.

FIG. 2(a) shows human input signals rt,,v, of a conventional circuit.

The output signal of the NAND gate 9 and the output signal LJ.

This is an example of the waveform of D. In the same figure,
When the human input signal R, is slightly earlier than the input signal V1 as shown by the dotted line, the output signal U1 is output as shown by the dotted line, but when they arrive at the same time, the output signals U + and D I are output as shown by the solid line.
is not output.

Therefore, the phase detection characteristic in which the integral difference between two pulses is used as the phase detection output has the drawback that a dead zone appears near the phase difference O as shown in FIG. 3(a), making PLL control unstable.

(Means for Solving the Problems) The present invention resets the arrival detection outputs of the two signals after they are fully saturated, and the reset signal that detects the arrival of the two signals is By not gate-synthesizing any of the two signal arrival detection outputs, the dead zone near the zero difference is eliminated, and the linearity of detection with respect to phase difference is further improved. Embodiments of the present invention will be described in detail below with reference to the drawings.

(Example) Figure 1 shows an example of the present invention with 1.2.3, 4°5.6,
7.8 and 9 are NΔAND gates, IO is a delay circuit, R
, and ■1 are input signals, U, and.

is the phase detection output.

The NAND gates I, 2.3, and 4 constitute a signal detection circuit 11, the NΔND gates 5, 6, 7, and 8 constitute another signal detection circuit 12, and the NΔND gate 9 and the delay circuit 10 constitutes a reset circuit 13.

Input signal R, 7>(NAND gate l when at H level
The output of NAND gate 3 becomes L level, and therefore, due to the operation of the SR flip-flop constituted by NAND gates 3 and 4, the output of NAND gate 3 becomes I level, and NAND gate 3 becomes L level.
The output U1 of the D gate 2 becomes H level.

Next, when the human power signal R0 goes to L level, the outputs of NAND gates 1 and 3 both go to H level, thereby detecting the signal. Also, at this time, the output Ul of the NΔAND gate 2 changes to the L1 novel.

Similarly, when the human input signal V changes from the [■] level to the L level, the outputs of the NAND gates 6 and 7 both go to the r+ level, thereby detecting the signal. Also, at this time, NAND
The output of gate 8 changes to L level.

With the arrival of the two signals, NAND gates 1 and 3
．． 6 and 7 both go to H level, the output of NAND gate 9 of reset circuit 13 changes to L level, which is delayed by delay circuit 10 and output to signal detection circuit 1.
1, I2 to the common reset terminal r- of NΔNl) and applied to gates 4 and 5 to operate the reset I.

The reset operation sets the outputs of NAN I) gates 3 and 6 to L level, and therefore the reset operation is canceled.
Also, the outputs U of NAND gates 2 and 8.

and both return to II lehel.

To delay the reset signal, buffer circuits are connected in multiple stages, or a delay circuit using R and c (resistance capacitors) is used.

With this configuration, phase detection characteristics with good linearity and no dead zone can be obtained as shown in FIG. 3(b).

Figure 2 (b) shows the phase detection output LJ when the input signal arrives slightly earlier than the input signal V1 (+3 "3" I?1).
The waveforms of + and -, the output waveform of the NΔAND gate 9 for reset detection, and the reset signal waveform after d delay are shown. Also shown is the case of simultaneous arrival, in which case the output signals tJ, , I) are output as shown by solid lines.

FIG. 4 shows another embodiment of the present invention, in which the reset signal (lj) is generated using a NOR gate for the circuit shown in FIG. 1. Since the individual operations are well known, their explanation will be omitted.

(Effects of the Invention) As explained below, according to the present invention, there is no dead zone.
Since phase detection characteristics with good linearity can be obtained, stable PT and L control is possible.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is an explanatory diagram of waveforms of each part, Fig. 3 is an explanatory diagram of horn characteristics for detection, Fig. 4 is another embodiment, and Fig. 5 is a conventional diagram. FIG. 10... Delay circuit, If, +2... A,) call detection circuit, 13... Reset circuit. Patent Applicant [I Honmusen Co., Ltd. 1 Figures 1-9 NAND Genit 1 Ing Detection Circuit 3 Each Plate 3 Figure 4 (a) Output Signal D1 Time Figure 2 (b) I

Claims (1)

[Claims] It has two signal detection circuits that detect and output the arrival of a signal, and a reset circuit that generates a reset signal in response to the arrival of a signal to both of the two signal detection circuits. In a phase detection circuit configured to repeatedly detect the arrival of two signals by resetting both, the reset circuit is provided with a delay circuit connected to a common reset terminal of the two signal detection circuits, and the delay circuit is connected to a common reset terminal of the two signal detection circuits. 1. A phase detection circuit characterized in that the outputs of the two signal detection circuits are both made to sufficiently reach a saturation level by a reset signal that has passed through the phase detection circuit.