JPH01125125A - Phase frequency comparator - Google Patents

Abstract

PURPOSE:To widen the input band and input sensitivity by inserting a waveform shaping circuit into the input terminal of two 2-input NOR gates or at the post-stage so as to eliminate the causes to malfunction due to the production of a transient state even if an input waveform changes slowly in comparison with the response speed of the gate. CONSTITUTION:Waveform shaping circuits 8, 9 are inserted into the pre-stage or post-stage of the input terminals of 1st and 2nd 2-input NOR gates 1, 2 or at the post-stage or a delay element 10 is inserted to the output of a 4-input NOR gate 5 in a phase frequency comparator(PFC) constituted to prevent malfunction and used in a phase locked loop(PLL). Thus, even if the input waveform of the 2-input NOR gates 1, 2 changes slowly in comparison with the response speed of the 4-input NOR gate 5, the normal operation is ensured and the spread of the input band and the input sensitivity is attained.

Description

Detailed Description of the Invention (1) Purpose of the Invention [Field of Industrial Application] The present invention relates to a phase frequency comparison circuit (RFC) with a malfunction prevention configuration used in a phase-locked loop (PLL).
It is related to.

[Prior Art] FIG. 5 shows a symbolic logic block diagram of a conventional PFC. The output of 2-input NOR gate 1 is connected to the reset terminal of flip-flop 3 with set/reset and 3-input OR/N
It is connected to the OR gate 6 and the 4-input NOR gate 50 input, and the output of the 2-input NOR gate 2 is connected to the reset terminal of the flip-flop 4 with set/reset and the 3-input OR/NOR
It is connected to the input of gate 7 and 4-input NOR gate 5, and the output of flip-flop 3 with set/reset is connected to 3-input O
A flip-flop 4 with set/reset is connected to the input of the R/NOR gate 6 and the input of the 4-input NOR gate 5.
The output of the 4-input OR/NOR gate 7 is connected to the input of the 4-input NOR gate 5, and the output of the 4-input NOR gate 5 is connected to the input of the 3-input OR/NOR gate 6.7 and the set/reset flip-flop 3, The NOR output of 3-input OR/NOR gate 6 is connected to the input of 2-input NOR gate 1, and the 3-input OR/NOR gate 6 is connected to the set terminal of 4.
The output of gate 7 is connected to the input of 2-input NOR gate 2, and the other input of 2-input NOR gate 1゜2 is connected to 2.
With two input terminals R and V, 3-input OR/NOR gate 6
．． 7 OR/N.

This is a configuration in which the R output is provided as four output terminals u, u, 'o, and v.

The function of this circuit is to detect the phase difference between the input signals applied to the input terminals R and V and output it to the output terminals U and D as a pulse length. Three types of timing diagrams are shown in FIG. 6 as operation examples.

In the same figure (aHb), the input signals of the input terminals R1 and V have the same frequency but different phase relationships.

In the case of (a), the input signal of ■ is at an illumination level (H)
The output terminal U generates a pulse output signal by detecting the timing (phase difference) from when the R input signal changes from H to L after changing from the low level (L) to the low level (L).

The output signal from the output terminal is fixed at H.

In case (b), conversely, the output signal of output terminal U is fixed at H, and the phase difference from when the input signal of π changes from H to L until the input signal of ■ changes from H to L is the output terminal. The output signal of ① is expressed as a pulse.

In addition, (C) is a case where the frequencies of the input signals of R and V are different, and the input frequency of the ball is 1.5 times the input frequency of The same pattern signal is repeatedly output with three periods (or two periods of the input signal to the input terminal V) as one period.

The pulse signal output from the output terminal (2) detects the phase difference from when the input signal (2) changes from H to L until the input signal (π) changes from H to L.

2-input NOR gate 1.2 and flip-flop with set (S) and reset (R) 3.4.4-input NOR which are basic circuits of PFC using emitter coupled circuit (ECL)
When each logic element with the symbol mark of gate 5 and 3-input OR/NOR gate 6.7 is realized in a concrete circuit, for example, FIGS. 7(a)(b)(c)(d)
) is the circuit shown. Here, Vcc is the high potential side power supply, V
Rl and VR2 are reference voltages, and Vcs is a current source base reference voltage. When a latch type flip-flop with SR with 12-stage series gates as shown in FIG. 7(b) is used as the flip-flop with SR 3.4, the following problems arise from the viewpoint of the circuit configuration. While the input signals of the S and R terminals remain at the intermediate level for a long time (long time compared to the response speed of the series gate), the output signal of the output terminal Q is fixed at the intermediate level or at either level due to noise etc. A situation arises where you end up doing this. Since the circuit operates digitally, the input signals at the S and R terminals are never at intermediate levels as a stable state, but the input signals at the input terminals R and V change sufficiently slowly compared to the response speed of the ECL circuit. (in the case of large rise and fall times), such a state may exist, albeit transiently.

FIG. 8 shows by simulation that malfunction occurs in the PFC circuit due to the occurrence of the above state. (a) is a case of normal operation, and (b) is a case of malfunction.

(a) shows the monitored waveforms of each node (■ to ■ in FIG. 5) when a 120 MHz pulse wave is input to the input terminal R and a 130 MHz sine wave is input to the input terminal ■. The parameters of the transistor used in the simulation are rT = 10G112 (VCE = 1
In V), the basic gate delay is about 1 oops, and the input changes quite slowly compared to the response speed of the gate. The waveform is divided into 5 upper and lower stages, the top stage is the signal waveform at the input terminal R0■, the second stage is the node ■■, the third stage is the node ■■, the fourth stage is the node ■, and the fifth stage is the signal waveform at the output terminal. It is. Detection of the phase difference is performed by D outputting a pulse during the period from when the input signal at input terminal V changes from L to H until the input signal at input h@child R changes to L-+H. The relative position of the waveform shifts in accordance with the input frequency difference between the terminals R and V, and the output signal pulse width at the output terminal increases accordingly. Therefore, input terminal R,
The same pattern output is repeated at a cycle that is the least common multiple of the input signal cycle of V, and one cycle of the pattern is shown in FIG. (b) shows the case where a 120 MHz sine wave is input to the input terminal R and a 130 MHz pulse wave is input to the input terminal It is recognized that there are some areas that have not been detected. In other words, when the third phase difference detection ends when the input signal at the input terminal R goes from high to high, the output signal at the output terminal remains old until the next time the input signal at the input terminal R goes from low to high. It is fixed at the oh level. A similar malfunction occurs in the next detection. - Fig. 8(C) is an enlarged view of a normally operating part (second phase difference detection) and a malfunctioning part (third phase difference detection). The logic timing for normal operation is shown below.

(I) The input signal at input terminal V changes from L to H.

↓ (It) As the passing signal of the node ■ changes to high, all inputs of the 3-input NOR gate 7 become low.

↓ (III) The output signal at the output terminal changes from L to H (phase difference detection starts) ↓ (TV) The input signal at the input terminal R changes from L to H.

(V) As the passing signal of the node ■ changes from H to L, all inputs of the 4-input NOR gate 5 become inactive.

↓ (Vl) When the passing signal of the node ■ changes from L to H, the latch type S-R flip-flop 3.4 is set.

↓ (Vl) Since the passing signals of the node ■■ both go from L to H, one input of the 3-input NOR gate 7 and two inputs of the 4-input NOR gate 5 go to H.

↓ (■) The output signal at the output terminal changes from H to L and the detection of the phase difference is completed), and the signal passing through the node ■ changes from H to L.
become.

At the timing (V) (Vl), the passing signal of the node ■■, that is, the R of the latch type flip-flop 3.

Although the input signal to the S terminal is transient, it may almost simultaneously reach a state close to the intermediate level (this situation is shown in Figure 8 (
The passing signal of node ■■ is also monitored in the fourth stage of C), and it can be understood that this kind of situation occurs.)
. The change in the signal passing through node ■ is delayed by the delay of the 4-input NOR gate 5 relative to the change in the signal passing through node ■, but
The slower the change in the signal passing through node (2), the longer the time that both are at the intermediate level, and the greater the possibility of malfunction. In the input cover turn of (a), the input signal of the input terminal R is a pulse, so the signal passing through the node ■ changes relatively quickly, so there is no problem, but in the input cover turn of (b), the input signal of the input terminal R is Since it is a sine wave, the signal passing through node ■ changes gradually. Therefore, even if the input frequency is the same, normal operation will occur in (a), and malfunction will occur in (b).

In the case of malfunction, the passing signal of node ■■ does not go from L to H at the same time at the timing (Vl), but the passing signal of node ■■ mentioned earlier is at an intermediate level, so node ■■
The passing signal changes from L to H more quickly. For this reason, the passing signal at node (2) does not go to the H side sufficiently but goes to L, so the flip-flop 4 with latch type R-8 cannot be set, and the passing signal at node (2) cannot be set to H. Therefore, the output signal at the output terminal does not reach its full potential, making it impossible to complete phase difference detection. What is characteristic of a malfunction compared to a normal operation is that the passing signals of the node ■■ do not go to H at the same time, and that the passing signal of the node ■ does not reach H completely and falls. In addition, the direct cause of the malfunction is that the signal passing through node ■ changes immediately following the change in the signal passing through node ■ (with a delay of only one gate stage), so that the RSS terminal of latch type flip-flop 4 simultaneously reaches the intermediate level. It is to become. Therefore, input is relatively low.
(Malfunction may occur when the frequency is a sine wave or when the amplitude of the input is small.Also, in this case, malfunction occurs only when the signal passing through node ■ changes slowly, but the circuit From the symmetry, it can be easily inferred that there are cases where a similar situation occurs for the signal passing through node (2), resulting in malfunction.

As described above, in the basic logical configuration of the RFC shown in FIG. 5, the conventional circuit to which the ECL circuit as shown in FIG. 7 is applied has the disadvantage of causing malfunctions.

[Problems to be Solved by the Invention] The present invention is a PFC circuit to which a conventional ECL circuit is applied, so that malfunctions that may occur due to timing can be solved by converting the conventional ECL circuit into a waveform shaping circuit or a delay line, especially a monolithic IC.
The present invention aims to provide an RFC circuit that eliminates the possibility of malfunctions and operates normally over a wide range by using delay gates.

2) Structure of the Invention [Means for Solving Problems] The phase frequency comparator of the present invention has the output of the first two-input NOR gate connected to the reset terminal of the first set/reset flip-flop and the first The first input of the 3-input OR/NOR gate is connected to the first input of the 4-input NOR gate, and the output of the second 2-input NOR gate is connected to the reset terminal of the second flip-flop with set/reset. The first input of the 3-input OR/NOR gate and the 4-input NOR
The output of the first set/reset flip-flop is connected to the second input of the gate, and the output of the first set/reset flip-flop is connected to the first three-input OR.
/NOR gate and the third input of the 4-input NOR gate, and the output of the second set/reset flip-flop is connected to the second 3-input OR/N
A second input of the OR gate and a fourth input of the 4-input NOR gate are connected, and an output of the 4-input NOR gate is connected to a third input of the first and second 3-input OR/NOR gates and a fourth input of the 4-input NOR gate. 1 and a second set/reset flip-flop, and the first three-input OR/NOR gate (7) NOR output is connected to the first input of the first two-input NOR gate. , said second 3
a NOR output of the input OR/NOR gate is connected to a first input of the second two-input NOR gate, second inputs of the first and second two-input NOR gates are two input terminals; In a phase frequency comparator configured with the OR/NOR outputs of the first and second 3-input OR/NOR gates as four output terminals, By inserting a waveform shaping circuit at the front or the rear, or by inserting a delay element at the output of the 4-input NOR gate, the input waveform of the 2-input NOR gate can be made gentler than the response speed of the 4-input NOR gate. This makes it possible to ensure normal operation even in cases where the input band and input sensitivity are widened.

[Embodiment] The above malfunction occurs when there is a transient state in which the input signals at the S and R terminals of the latch type set/reset flip-flop 3.4 are both at intermediate levels. This is due to the fact that the signal passing through the node ■ changes relatively slowly and the signal passing through the node ■ follows the change in the signal passing through the node ■ (or ■) with a delay of one gate stage. Therefore, by making circuit improvements, it is possible to speed up the change in the signal passing through node ■ (or ■) (that is, shorten the rise and fall times of the waveform), or to slightly delay the timing of the change in the signal passing through node ■ with respect to the signal passing through node ■. All you have to do is do it.

An embodiment of the invention will be described with reference to FIG.

Figures (a) and (b) show the first and second embodiments, in which a waveform shaping circuit 8.9 is used to speed up the rise and fall of the waveform of the signal passing through the node (2). In (a), waveform shaping is performed on the input signal waveforms of input terminals R and V, and in (b), waveform shaping is performed on the passing signal waveform of nodes ■■. Waveform shaping circuit 8
．． 9 is a normal ECL as shown in Figure 3 or Figure 4.
It consists of a buffer circuit or a Schmitt trigger circuit. (C) is a third embodiment, in which a delay circuit 10 is used to adjust the timing of the change in the signal passing through the node.
In this example, a delay buffer gate is inserted into the output of a 4-input NOR gate 5. The delay buffer 1 gate can be constructed from a circuit similar to the waveform shaping circuit 8.9 shown in FIG. 3 or 4, and it is also possible to use a delay caused by wiring.
When considering application to a monolithic IC, using a gate delay is advantageous in terms of area and effectiveness. Further, as other embodiments, a configuration in which (a), (b), and (C) are combined can be easily inferred.

[Function] Since the present invention is configured as described above, the timing diagram of the operating waveforms in the circuit of FIG. 1(C) is shown in FIG. 2(C).
Figures a), (b), and (c) show the results of simulation under the same conditions as in Figure 8.

That is, it can be seen that the phase difference in FIG. 2(b) is accurately detected even for the same input cover turn as in FIG. 8(b). In Fig. 2 (C), the level at which the passing signals of nodes ■ and ■ intersect is quite close to the L level, and it is clear that the latch type S/°R flip-flop 4 is prevented from malfunctioning. be. Regarding the sensitivity to input amplitude, for example, for the input cover turn shown in Fig. 8(a), the conventional configuration shown in Fig. 5 has an input amplitude of 0.4 V.
2.4v is possible for normal operation, but in this example, 0.2v is possible.
Normal operation is possible at v~3.4v, and the operating range of input amplitude can be greatly expanded.

(3) Effects of the Invention Thus, in the conventional RFC circuit configuration using an ECL circuit, when the input waveform changes slowly compared to the response speed of the gate, the RFC circuit according to the present invention has an internal S-R flip-flop. This eliminates the cause of malfunctions caused by transient conditions where both the S and R terminals of the circuit are near intermediate levels, allowing normal operation even when the input waveform is slow relative to the response speed of the circuit. It has excellent effects such as widening the band and input sensitivity.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) are sympolink circuit diagrams showing the first to third embodiments of the present invention, and FIG. 2(a)(
b) and (c) are timing diagrams of the simulation operation waveforms, Figure 3 is a buffer circuit using ECL, Figure 4 is a Schmitt trigger circuit using ECL, and Figure 5 is a symbolic basic logic diagram of the RFC circuit. , Fig. 6 (a), (b), and (c) are respective timing diagrams of the same operation waveform, and Fig. 7 (aHb) (c) (
d) is a diagram of each constituent iQf element with symbol marks and each realized by an ECL circuit, Fig. 8(a)(b)(c)
) Figure 7 (a) (b) (c)
3 is a timing diagram of each simulation operation waveform when applied to a circuit. 1.2...2-input NOR gate 3.4...Flip-flop with set/reset 5.
...4-input NOR gate 6.7...3-input OR/NOR gate 8.9...Waveform shaping circuit 10...Delay circuit R, V...Input terminals u, U, o, T...・Output terminal)

Claims (1)

[Claims] 1. The output of the first two-input NOR gate is connected to the first set of
Reset terminal of flip-flop with reset and first 3
The first input of the input OR/NOR gate is connected to the first input of the 4-input NOR gate, and the output of the second 2-input NOR gate is connected to the reset terminal of the second set/reset flip-flop and the second input of the 4-input NOR gate. The first input of the 3-input OR/NOR gate is connected to the second input of the 4-input NOR gate, and the output of the first set/reset flip-flop is connected to the first input of the 3-input OR/NOR gate. The output of the second set/reset flip-flop is connected to the second input of the second three-input OR/NOR gate and the third input of the four-input NOR gate. The output of the 4-input NOR gate is connected to the fourth input of the input NOR gate, and the output of the 4-input NOR gate is connected to the 4-input NOR gate.
The third input of the input OR/NOR gate is connected to the set terminals of the first and second set/reset flip-flops, and the NOR output of the first three-input OR/NOR gate is connected to the first two flip-flops. an input NOR gate, a NOR output of the second 3-input OR/NOR gate is connected to a first input of the second 2-input NOR gate, and a In the phase frequency comparator, the second input of the two-input NOR gate is configured as two input terminals, and the OR/NOR outputs of the first and second three-input OR/NOR gates are configured as four output terminals. A phase frequency comparator 2 characterized in that a waveform shaping circuit is inserted at the input terminal side of the first and second two-input NOR gates or at a subsequent stage, the output of the first two-input NOR gate is a first set,
Reset terminal of flip-flop with reset and first 3
The first input of the input OR/NOR gate is connected to the first input of the 4-input NOR gate, and the output of the second 2-input NOR gate is connected to the reset terminal of the second set/reset flip-flop and the second input of the 4-input NOR gate. The first input of the 3-input OR/NOR gate is connected to the second input of the 4-input NOR gate, and the output of the first set/reset flip-flop is connected to the first input of the 3-input OR/NOR gate. 2 and a third input of the four-input NOR gate;
An output of the second set/reset flip-flop is connected to a second input of the second 3-input OR/NOR gate and a fourth input of the 4-input NOR gate,
The output of the input NOR gate is connected to the third input of the first and second three-input OR/NOR gates and the first and second three-input OR/NOR gates.
is connected to the set terminal of the flip-flop with set/reset, and is connected to the NO of the first 3-input OR/NOR gate.
R output is connected to the first input of the first two-input NOR gate, and the R output is connected to the first input of the first two-input NOR gate;
R output is connected to a first input of the second two-input NOR gate, the second inputs of the first and second two-input NOR gates are two input terminals, and the first and second
A phase frequency comparator configured with OR/NOR outputs of a 3-input OR/NOR gate as four output terminals, characterized in that a delay element is inserted into the output of the 4-input NOR gate.