JPH0474979A - Test mode setting circuit of integrated circuit - Google Patents

Abstract

PURPOSE:To set up a test mode with only one outside input terminal by adding an outside input signal detecting circuit which selects an outside input signal and outputs a selected signal in a test mode time, inputting the outside input signal and an inside reset signal in a test mode setting circuit having a signal selecting circuit. CONSTITUTION:An integrated circuit 10 is provided with an outside input signal detecting circuit 4 and a signal selecting circuit 5. A signal S1 of an outside input terminal 1 is made '0' level at the first point of time t0. Next, the signal S1 is made '1' level at the point of time t2 after a highly active wave form is inputted as a signal S3 from an inside reset end 3 at the point of time t1. An output signal SQ of the detecting circuit 4 becomes '1' level, the '1' of the signal S1 is outputted to an output signal S6 and a test mode is formed. The test mode is released as follows: the signal S3 is made '1' level and the signal SQ '0' level after the signal S1 of the outside input terminal 1 is made '0' level.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a test mode setting circuit for integrated circuits.

[Conventional technology]

Generally, a test mode setting circuit that inputs a signal from the outside for testing the internal circuit of an integrated circuit has at least two external terminals, a signal input terminal and a test mode setting terminal, and a test mode setting circuit that inputs a signal to the test mode setting terminal. A function is required to select either an external input signal or an internal input signal and output it to the internal circuit.

FIG. 6 is a block diagram of an example of a conventional integrated circuit test mode setting circuit.

As shown in FIG. 6, the signal input terminals Inl and In2 of the signal selection circuit 5 of the integrated circuit 10b each have an external input terminal 1.
and the internal signal terminal 2 are connected, and the test mode setting terminal 9 from the outside is connected to the signal selection terminal S, and by this test mode setting signal s9, either Inl or In, 2 is input to the internal output terminal 6. A signal is output.

There are two external terminals at this time: external input terminal 1 and test mode setting terminal 9.

[Problem to be solved by the invention]

In the conventional integrated circuit test mode setting circuit, 1
If two external input terminals are provided, one or more test mode setting terminals must also be provided, which has the disadvantage that a test mode setting circuit cannot be incorporated when the number of external terminals must be reduced due to IC package limitations. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test mode setting circuit for an integrated circuit that can set a test mode using only one external input terminal.

[Means to solve the problem]

The test circuit of the present invention has a signal selection circuit that inputs a selection signal and selects either an external input signal or an internal input signal from an external input signal terminal, and in a test mode, selects the external input signal and selects the internal input signal from the external input signal terminal. In the test mode setting circuit of the integrated circuit supplied to the circuit, an external input signal detection circuit is added which inputs the external input signal and the internal reset signal and selects the external input signal and outputs the selection signal when in the test mode. It is composed of

Further, the external input signal detection circuit includes an RS flip-flop.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a truth diagram of the external input signal detection circuit 4 of FIG. 1, and FIG. 3 is a block diagram of the input signal of the block of FIG. 1. FIG. 3 is a timing diagram of signals.

In FIG. 1, the external input signal detection circuit 4 inputs an external input signal S1 to the R terminal, an internal reset signal to the S terminal, and outputs an output signal SQ from the Q terminal so as to perform the logical operation shown in FIG. The signal selection circuit 5, which is composed of flip-flops and is the same as the conventional example shown in FIG. 6, selects the input terminal In1 when the input terminal S is at the "1" level, and selects the input terminal In2 when the input terminal S is at the "0" level. The input terminal Inl receives an external input signal S1, and the input terminal In2 receives an internal signal S2.
is supplied to the terminal S, and the Q of the external input signal detection circuit 4 is supplied to the terminal S.
The ends are connected.

In order to determine the initial value, the signal S1 of the external input terminal 1 is set to the "0" level at the first time point to, and the signal S3 from the internal reset terminal 3 is set to the high active level at the time point t1 as shown in FIG. After inputting the waveform, when the first 1" level signal S1 is input from the external input terminal 1 at time t2, the output signal S from the Q terminal of the external input signal detection circuit 4
Q becomes “1” level, and output terminal 6 is connected to external input terminal 1.
"1'° of the signal S1 from 1" is output as the output signal S6, and the test mode is set.

To cancel the test mode setting, set the signal S1 of the external input terminal 1 to the "0" level at all times, and then set the signal S3 of the internal reset terminal 3 to the "1" level. The output signal SQ becomes "0" level and the test mode setting can be canceled.

FIG. 4 is a block diagram of a second embodiment of the present invention, and FIG. 5 is a timing diagram of input signals of the blocks of FIG.

Instead of the external input signal detection circuit 4 in FIG. An external input signal detection circuit 4a is provided which has an OR circuit 7 and an AND circuit 8 whose two input terminals each receive an OR output signal and an internal reset signal S3 and output an AND output signal S8.

As shown in FIG. 5, after the signal S3 of the internal reset terminal 3 is set to the "1" level, the external input terminal 1 becomes the first "1" level at time t2, and at the same time, the AND output signal S8 of the AND circuit 8 is also set to the "1" level. Since the output signal S7 of the OR circuit 7 is at the "1" level no matter what signal S1 is input from the external input terminal 1 after that, the signal selection circuit 5 selects Inl, and the output terminal 6 The signal S1 from the external input terminal 1 is output as the signal S6.

To cancel the test mode setting, first set external input terminal 1 to “O” level, then turn internal reset signal S3 to “0”.
When set to the blank level, the output signal S7 of the OR circuit 7 is °″0'
``0'' Levelest mode can be canceled.

With this configuration, one external input terminal 1
You can set the integrated circuit test mode with

〔Effect of the invention〕

As is clear from the above explanation, according to the test mode setting circuit for an integrated circuit of the present invention, when a test mode setting circuit provided with one external input terminal is incorporated, one external terminal is not provided for setting the test mode. This has the effect of incorporating a test mode setting circuit using the external input terminal.

5 is a timing diagram of input signals for explaining the operation of the block in FIG. 4, and FIG. 6 is a block diagram of an example of a conventional test circuit.

1... External input terminal, 2... Internal signal terminal, 3...
Internal reset terminal (high active), 4. ．． 4a...
External input signal detection circuit, 5... Signal selection circuit, 6...
・Internal output terminal, 7...OR circuit, 8...AND circuit, 9...test mode setting terminal, 10.10a...
Integrated circuit, Sl...external input signal, SQ, S7. S9
...Selection signal, S3...Internal reset signal.

Claims (1)

[Claims] 1. A signal selection circuit that inputs a selection signal to select either an external input signal from an external input signal terminal or an internal input signal, and selects the external input signal in a test mode. In the integrated circuit test mode setting circuit that supplies the internal circuit, an external input signal detection circuit is added that inputs the external input signal and the internal reset signal, selects the external input signal in the test mode, and outputs the selection signal. A test mode setting circuit for integrated circuits. 2. The integrated circuit test mode setting circuit according to claim 1, wherein the external input signal detection circuit includes an RS flip-flop.