JPH0627204A - Test mode setting system for integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a test mode setting system for integrated circuit in which a test mode can be set for an integrated circuit having a plurality of functions through the use of a single external terminal. CONSTITUTION:When a test mode is set, predetermined ones of internal registers 1-1a, 1-2a,...1-na, provided for the function blocks 1-1, 1-2,...1-n of an integrated circuit 1 in order to set the essential function of respective blocks, are set in a predetermined state and then a test mode set signal is inputted through a test mode set terminal 3. A logic circuit 2 performs logical operation on the outputs from the internal registers 1-1a, 1-2a,...1-na and a test mode set signal inputted through the test mode set terminal 3 and sets a predetermined block in test mode based on the output therefrom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode setting method for an integrated circuit having a plurality of functional blocks that are not related to each other, and more particularly, the present invention sets a test mode for a plurality of functional blocks inside the integrated circuit. The present invention relates to an integrated circuit test mode setting method that can be performed with one terminal.

[0002]

2. Description of the Related Art An integrated circuit is usually provided with a test mode setting terminal, and when testing the internal function of the integrated circuit, the function, mode, etc. of the integrated circuit to be tested are set from the test mode setting terminal. And are testing. Conventionally, when testing an integrated circuit having a plurality of functional blocks, test terminals corresponding to the required number of tests are provided, internal registers and decoders dedicated to test mode setting are provided, and testing is performed externally. I was testing by setting functional blocks, test modes, etc.

[0003]

By the way, as described above, when the test terminals are provided according to the required number of tests, the number of external terminals corresponding to the function inside the integrated circuit and the test mode is provided. It is necessary, especially in an integrated circuit having multiple functional blocks inside the integrated circuit,
It is necessary to provide many external terminals for setting the test mode, which has a drawback of increasing the package size.

Further, when the internal register and the decoder dedicated to the test mode setting are provided as described above, the number of external terminals for setting the test mode can be reduced as compared with the above, but the internal register can be reduced. In addition to requiring multiple external pins to set the internal circuit, it is necessary to provide an internal register and decoder for the test mode setting inside the integrated circuit, which increases the package size and complicates the internal configuration. There was a drawback that

The present invention has been made in view of the above-mentioned drawbacks of the prior art. An integrated circuit test capable of setting a test mode of an integrated circuit having a plurality of functions by using only one external terminal. -The purpose is to provide a mode setting method.

[0006]

FIG. 1 is a basic configuration diagram of the present invention. In the present invention, in order to solve the above-mentioned problems, a plurality of functional blocks 1 that are not functionally related to each other are provided.
Test of integrated circuit 1 including -1,1-2, ... 1-n
In the mode setting method, one test
The mode setting terminal 3 is provided, and the plurality of functional blocks 1-1, 1-2, ... 1-n are provided inside the integrated circuit 1.
Internal registers 1-1a, 1-2a, ...
A logic circuit 2 for performing a logical operation between the output of 1-na and the test mode setting terminal 3 is provided, and a specific one of a plurality of functional blocks 1-1, 1-2, ... 1-n of the integrated circuit 1 is provided. When setting the functional block to the test mode, a signal is input from the external terminal to input the internal registers 1-1a, 1-
A specific internal register of 2a, ... 1-na is set to a predetermined state, a test mode setting signal is input from the test mode setting terminal 3, and a plurality of functional blocks 1 are output by the output of the logic circuit 2. -1,1-2, ... 1-n
It is configured to set a specific function block in the test mode to the test mode.

[0007]

When the desired function block among the function blocks 1-1, 1-2, ... 1-n is set to the test mode,
Tests by setting a predetermined internal register among the internal registers 1-1a, 1-2a, ... 1-na provided inside the functional blocks 1-1, 1-2, ... 1-n to a predetermined state.・
Input the test mode setting signal from the mode setting terminal 3.

The logic circuit 2 includes internal registers 1-1a, 1-
The output of 2a, ... 1-na and the test mode setting signal from the test mode setting terminal 3 are logically operated, and a predetermined functional block is set to the test mode by the output. Using the outputs of the internal registers 1-1a, 1-2a, ... 1-na and the test mode setting signal input from the external terminals, a plurality of functional blocks 1-in the integrated circuit 1
Since 1, 1-2, ... 1-n are set to the test mode, a plurality of test modes can be set by one test mode setting terminal, and the test mode is set. The configuration of the gate circuit can be simplified.

[0009]

FIG. 2 is a diagram showing one embodiment of the present invention. In FIG. 2, 11 is an integrated circuit, and a plurality of functional blocks 12, 13, 14 are provided therein. 12, 1
Reference numerals 3 and 14 denote an A function block, a B function block, and a C function block inside the integrated circuit 11, respectively, and these functions are independent functions and have no functional relationship with each other. The A and B functional blocks 12 and 13 are provided with test setting inputs XTESTA and XTESTB for setting the respective functional blocks into a test mode, and the C functional block 14 is provided with two types of first and second test modes. Set test mode setting input XTE
It has STC1 and XTESTC2. In addition, these test mode setting inputs XTESTA, XTEST
B, XTESTC1, and XTESTC2 are active low, and when their values are low, their respective test modes are set.

Also, the A, B and C functional blocks 12,
Input and output of 13 and 14 are connected by a common bus, and are connected to external terminals of the integrated circuit 11. 12a, 13a,
14a is an A, B and C functional block 12, 13, 1
The first, second, and third units provided to set the original function of the fourth unit (for example, to set its control mode, etc.)
The internal register of the integrated circuit 11 can be set from an external terminal of the integrated circuit 11. Further, as described above, since the respective function blocks 12, 13, 14 are functionally independent, the respective function blocks 12, 13, 1 are normally operated.
4 output XQ of internal registers 12a, 13a, 14a
A, XQB, and XQC do not affect the functions of other functional blocks.

The internal registers 12a, 13a, 14
The outputs XQA, XQB, and XQC of a are active low, and their values are low level when set. G1, G
2, G3 and G4 are OR gates, T1 is a test mode setting external terminal of the integrated circuit 11, and a test mode setting signal XTEST is externally applied to its input.
The test mode setting signal XTEST is the output XQA, XQB, XQ of the internal registers 12a, 13a, 14a.
Similar to C, it is active low, and its value becomes low level when set.

In addition, the test mode setting external terminal T1
Is connected to one input terminal of the OR gates G1, G2, G3 and G4, and the other input terminals of the OR gates G1, G2, G3 and G4 are connected to the first, second and third internal registers 12 respectively.
The outputs of a, 13a, and 14a are connected. The output of the OR gate G1 is connected to the test mode setting input XTESTA of the A function block 12, and the output of the OR gate G2 is the test mode setting input X of the B function block 13.
Connected to TESTB and also OR gates G3 and G4
2 are connected to the test mode setting inputs XTESTC1 and XTESTC2 of the C function block 14, respectively.

FIG. 3 shows each functional block 12 in FIG.
13 is a flowchart showing a procedure for setting the test modes 13 and 14 in the test mode. FIG.
Is set to the test mode, the same figure (b) is to set the B functional block 13 to the test mode, and the same figure (c) is to set the C functional block 14 to the first and second test modes. The procedure for setting the C function block 14 in the second test mode is shown in FIG.

Next, referring to the flowchart of FIG.
The setting of the test mode of the embodiment shown in FIG. When setting the A function block 12 in the test mode, as shown in FIG. 3A, in step S1, the C function block 1 is set from the external setting terminal of the integrated circuit 11.
4 asserts the third internal register 14a, sets its output XQC to a low level, and in step S2, the second setting of the B functional block 13 is performed from the external setting terminal of the integrated circuit 11.
Asserts the internal register 13a and sets its output XQB to low level.

Next, in step S3, when the external input terminal XTEST of the integrated circuit 11 of FIG. 2 is set to the low level, the inputs of the OR gate G1 are all set to the low level, and the output thereof is set to the low level. test·
Mode setting input XTESTA goes low,
The test mode of the function block 12 is set. When setting the B function block 13 to the test mode,
As shown in FIG. 3B, in step S1, the first setting of the A function block 12 is performed from the external setting terminal of the integrated circuit 11.
Of the integrated circuit 11a of the integrated circuit 11a
The third internal register 14a of the C function block 14 is asserted from the external setting terminal of the above, and its output XQC is set to the low level.

Then, in step S3, when the external input terminal XTEST of the integrated circuit 11 of FIG. 2 is set to the low level, the inputs of the OR gate G2 are all set to the low level, and the output thereof is set to the low level. test·
Mode setting input XTESTB goes low, and B
The test mode of the function block 13 is set. When setting the C function block 13 in the first and second test modes, as shown in FIG.
1 asserts the first internal register 12a of the A functional block 12 from the external setting terminal of the integrated circuit 11,
The output XQA is set to the low level, and in step S2, the B function block 1 is supplied from the external setting terminal of the integrated circuit 11.
The second internal register 13a of No. 3 is asserted, and its output XQB is set to low level.

Next, in step S3, when the external input terminal XTEST of the integrated circuit 11 of FIG. 2 is set to low level, the inputs of the OR gates G3 and G4 are all set to low level.
Since it becomes a level, its output becomes a low level, and the test mode setting inputs XTESTC1, XTESTC2
Goes low, and the first and second test modes of the C function block 14 are set.

When the C function block 13 is set to the second test mode, as shown in FIG. 3D, in step S1, the B function block 13 is connected to the external setting terminal of the integrated circuit 11. Second internal register 13a
Is asserted and its output XQB is set to low level.
Then, in step S2, when the external input terminal XTEST of the integrated circuit 11 of FIG. 2 is set to low level, the inputs of the OR gate G4 are all set to low level.
Its output goes low, the test mode setting input XTESTC2 goes low, and the second test mode of the C function block 14 is set.

In the above embodiment, when the A function block 12 and the B function block 13 are set to the test mode, and when the C function block 14 is set to the first and second test modes and the second test. Although the case of setting the mode has been described, the present invention is not limited to the above embodiment, and it is possible to set an arbitrary test mode by changing the connection configuration of the gates G1 to G4. is there. In addition, the internal registers 12a, 1
The setting order of 3a and 14a is not limited to the above embodiment, and the test mode can be set in the same manner even if the setting order is changed.

[0020]

As is apparent from the above description,
In the present invention, the output of the internal register provided inside the integrated circuit for setting the original function of the plurality of functional blocks and the test mode setting signal input from the external terminal are provided. Since a plurality of functional blocks inside the integrated circuit are set in the test mode by using the test mode, a plurality of test modes can be set by one test mode setting terminal and the test mode can be set.
The configuration of the gate circuit for mode setting can be simplified.

Therefore, the structure of the integrated circuit can be simplified, and the package size can be reduced, which has a great practical effect.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a diagram showing an example of the present invention.

FIG. 3 is a flowchart showing a procedure for setting a test mode.

[Explanation of symbols]

1, 11 integrated circuit 1-1, 1-2, 1-n, 12, 13, 14 functional block 1-1a, 1-2a, 1-na, 12a, 13a, 14
a Internal register 2 Logic circuit 3, T1 Test mode setting external terminal G1, G2, G3, G4 OR gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/82

Claims (1)

[Claims] 1. A test mode setting method for an integrated circuit (1) comprising a plurality of functional blocks (1-1, 1-2, ... 1-n) that are not functionally related to each other. 1) One test mode setting terminal (3) is provided, and inside the integrated circuit (1), the multiple functional blocks (1-1, 1-2)
… 1-n) has internal registers (1-1a, 1-2a,… 1-
na) and a logic circuit (2) that performs a logical operation between the test mode setting terminal (3) and a plurality of functional blocks (1-1, 1-2, ... 1-of the integrated circuit (1). When setting a specific function block in (n) to the test mode, input a signal from the external terminal and set the internal register (1-1a, 1-
2a, 1-na), set a specific internal register to a specified state, input a test mode setting signal from the test mode setting terminal (3), and output it from the logic circuit (2). Multiple functional blocks (1-
An integrated circuit test mode setting method characterized by setting a specific functional block among 1,1-2, ... 1-n) to the test mode.