JPS61166155A - Cmos semiconductor device - Google Patents
Cmos semiconductor deviceInfo
- Publication number
- JPS61166155A JPS61166155A JP60007814A JP781485A JPS61166155A JP S61166155 A JPS61166155 A JP S61166155A JP 60007814 A JP60007814 A JP 60007814A JP 781485 A JP781485 A JP 781485A JP S61166155 A JPS61166155 A JP S61166155A
- Authority
- JP
- Japan
- Prior art keywords
- well region
- type well
- drain regions
- source
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- -1 phosphorus ions Chemical class 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はＣＭＯＳ半導体装置、特に高速動作に適するＣ
ＭＯＳ半導体装置に関する。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to CMOS semiconductor devices, particularly CMOS semiconductor devices suitable for high-speed operation.
It relates to a MOS semiconductor device.
（ロ）従来の技術
ＣＭＯＳ半導体装置は低消費電力であり、耐雑音特性も
秀れ、設計も容易であり、ＮＭＯ８半導体装置よりも優
れているため、今後ＶＬＳＩ用の素子として有望である
。しかしながら高速動作についてはＮＭＯ８半導体装置
に比べて一歩譲っていた。(b) Conventional technology CMOS semiconductor devices have low power consumption, excellent noise resistance, are easy to design, and are superior to NMO8 semiconductor devices, so they are promising as elements for VLSI in the future. However, in terms of high-speed operation, it was one step inferior to the NMO8 semiconductor device.
従来のＣＭＯＳ半導体装置を第２図に示す。（２１）は
Ｎ型シリコン基板であり、（２暗家深さ５μｍ程のＰ型
ウェル領域であり、（２３１はＰ型ウェル領域（２２１
より浅いＮ型ウェル領域であり、（２４）（２５１＆ま
Ｐ型ウェル領域（２り内に形成されるＮチャンネルＭＯ
Ｓトランジスタのソースおよびドレイン領域であり、（
イ）＋＋２７）はＮ型ウェル領域（２３）内に形成され
るＰチャンネルＭＯＳトランジスタのソースおよびドレ
イン領域であり、（２８）（２９）＆−ｉポリシリコン
より成る各ＭＯ３）ランジスタのゲート電極であり、（
３０）はＰ 型のガード領域である。A conventional CMOS semiconductor device is shown in FIG. (21) is an N-type silicon substrate, (2 is a P-type well region with a depth of about 5 μm, and (231 is a P-type well region (221
This is a shallower N-type well region, (24) (251 & N-channel MO formed within the P-type well region (2)
These are the source and drain regions of the S transistor, (
b) ++27) are the source and drain regions of the P-channel MOS transistor formed in the N-type well region (23), and the gate electrodes of each MO3) transistor made of (28) (29) &-i polysilicon. can be,(
30) is a P type guard region.
Ｐ型ウェル領域（２２）はＮチャンネルＭＯＳトランジ
スタが１Ｖ前後のスレッショルド電圧を得るために必要
な表面濃度に形成され、Ｎ型ウェル領域（ハ）はパンチ
スルーを防止するために必要な表面濃度に形成されてい
る。The P-type well region (22) is formed with a surface concentration necessary for the N-channel MOS transistor to obtain a threshold voltage of around 1V, and the N-type well region (c) is formed with a surface concentration necessary to prevent punch-through. It is formed.
斯上したＣＭＯＳ半導体装置の従来例としては特公昭５
５−４８４６０号公報が挙げられる。この公報の第１図
ｊにはＰチャンネル間Ｏ８）ランジスタのソースおよび
ドレイン領域（２６＋（２７）より深いＮ型ウェル領域
（２３１が示されている。A conventional example of the above-mentioned CMOS semiconductor device is the
5-48460 is mentioned. FIG. 1j of this publication shows an N-type well region (231) deeper than the source and drain regions (26+(27)) of a P-channel (O8) transistor.
（ハ）発明が解決しようとする問題点
しかしながら斯る従来のＣＭＯＳ半導体装置ではＮ型ウ
ェル領域（２３）をＰチャンネル間Ｏ８）ランジスタの
ソースおよびドレイン領域（２６＋ （２７）より深（
形成しているので、ソースおよびドレイン領域（２６）
（２７）とＮ型ウェル領域（ハ）間で比較的高不純物濃
度のＰＮ接合が形成される。このためソースおよびドレ
イン領域＋２６）Ｕ７）の接合容量は比較的大きく形成
され、パルス入力に対する立上りあるいは立下りがこの
接合容量のためにだれてしまい、高速スイッチング動作
を行なえない欠点があった。(c) Problems to be Solved by the Invention However, in such a conventional CMOS semiconductor device, the N-type well region (23) is located between the P-channel (O8) and the source and drain regions (26+ (27)) of the transistor deeper (
Since the source and drain regions (26) are formed
A PN junction with a relatively high impurity concentration is formed between (27) and the N-type well region (c). For this reason, the junction capacitance of the source and drain regions +26)U7) is formed relatively large, and the rise or fall of a pulse input is delayed due to this junction capacitance, resulting in a drawback that high-speed switching operation cannot be performed.
に）問題点を解決するだめの手段
本発明は断点に鑑みてなされ、Ｎ ｆｌｌｊウェル領域
（３）をＰチャンネル間Ｏ８）ランジスタのソースおよ
びドレイン領域（６）（７）より浅く形成することによ
りソースおよびドレイン領域（６）（力の接合容量を大
巾に低減して高速スイッチング動作に適したＣＭＯＳ半
導体装置を実現するものである。B) Means for solving the problem The present invention has been made in view of the problem, and the N flj well region (3) is formed to be shallower than the source and drain regions (6) and (7) of the transistor between the P channels. This significantly reduces the junction capacitance of the source and drain regions (6), thereby realizing a CMOS semiconductor device suitable for high-speed switching operation.
（（ホ）作用
本発明に依るＣＭＯＳ半導体装置ではＮ型ウェル領域（
３）をＰチャンネルＭＯＳトランジスタのソースおよび
ドレイン領域（６）（力より浅く形成し、ソースおよび
ドレイン領域（６）（力の底面での接合容量を低減して
高速スイッチング動作を得ている。((e) Effect) In the CMOS semiconductor device according to the present invention, the N-type well region (
3) are formed shallower than the source and drain regions (6) of the P-channel MOS transistor, and the junction capacitance at the bottom of the source and drain regions (6) is reduced to obtain high-speed switching operation.
（へ）実施例
本発明に依るＣＭＯＳ半導体装置の一実施例を第１図に
示す。（１）はＮ型シリコン基板であり、（２）は深さ
約５μｍのＰ型ウェル領域であり、（３）は本発明の特
徴とするＮ型ウェル領域であり、ｆ４）（５）はＰ型ウ
ェル領域（２）内に離間されて形成されるＮチャンネル
ＭＯＳトランジスタを構成するソースおよびドレイン領
域であり、（６）（力はＮ型ウェル領域（３）に形成さ
れるＰチャンネル間Ｏ８）ランジスタのソースおよびド
レイン領域であり、（８１（９）は夫々のＭＯＳ）ラン
ジスタのチャンネル領域（１０）ＣＩ ］）上に形成さ
れたポリシリコンより成るゲート電極であり、圓はＰ型
ウェル領域（２）を取り囲むＰ 型のガード領域である
。(F) Embodiment An embodiment of a CMOS semiconductor device according to the present invention is shown in FIG. (1) is an N-type silicon substrate, (2) is a P-type well region with a depth of approximately 5 μm, (3) is an N-type well region that is a feature of the present invention, and f4) and (5) are These are the source and drain regions constituting an N-channel MOS transistor formed spaced apart in the P-type well region (2), and ) are the source and drain regions of the transistor, (81 (9) are the respective MOS), are the gate electrode made of polysilicon formed on the channel region (10) CI ]) of the transistor, and the circle is the P-type well region. This is a P type guard region surrounding (2).
本発明の特徴はＮ型ウェル領域（３）にある。Ｎ型ウェ
ル領域（３）はＰ型ウェル領域（２）を除く基板（１）
の略全面にリンイオンを選択的にイオン注入して形成さ
れる。具体的にはリンイオンをドーズ量１×１０′２個
・ｃｒｎ−２で加速電圧１５０ＫｅＶで注入を行い、深
さ約Ｏ１６μｍまでドライブインして形成する。このＮ
型ウェル領域（３）にはＰチャンネル間Ｏ８）ランジス
タを構成するソースおよびドレイン領域（６）（力を選
択拡散して形成し、ソースおよびドレイン領域（６）（
力はＮ型ウェル領域（３）より同じかやや深く形成する
ことに特徴かある。A feature of the present invention is the N-type well region (3). The N-type well region (3) is the substrate (1) except for the P-type well region (2).
It is formed by selectively implanting phosphorus ions into substantially the entire surface of the substrate. Specifically, phosphorus ions are implanted at a dose of 1.times.10'2 crn-2 at an acceleration voltage of 150 KeV, and are driven in to a depth of about 16 .mu.m. This N
The type well region (3) is formed by selectively diffusing the source and drain regions (6) (formed by selective diffusion of force) constituting the P-channel O8 transistor.
It is characteristic that the force is formed to be the same or slightly deeper than the N-type well region (3).
斯る本発明の構造に依れば、ＰチャンネルＭＯＳトラン
ジスタのソースおよびドレイン領域（６）（７）の底面
は第１図からも明らかな様に不純物濃度の高いＮ型ウェ
ル領域（３）とは接しないので、ソースおよびドレイン
領域（６）（７）の接合容量をその底面分については大
巾に低減できる。具体的には本発明と同一条件でイオン
注入してＮ型ウェル領域（３）を形成した従来の構造で
は接合容量は２ Ｘ １０−８Ｆ／ｃＩ！であったが、
本発明の構造では１．２Ｘ１０’Ｆ／、ｆｆｌと４０％
も接合容量を低減できるのである。According to the structure of the present invention, the bottom surface of the source and drain regions (6) and (7) of the P-channel MOS transistor is an N-type well region (3) with a high impurity concentration, as is clear from FIG. Since they are not in contact with each other, the junction capacitance of the source and drain regions (6) and (7) can be greatly reduced at their bottom surfaces. Specifically, in the conventional structure in which the N-type well region (3) was formed by ion implantation under the same conditions as the present invention, the junction capacitance was 2 x 10-8 F/cI! However,
In the structure of the present invention, 1.2X10'F/, ffl and 40%
Also, the junction capacitance can be reduced.
この結果Ｎ型ウェル領域（３）に形成するＰチャンネル
ＭＯ５）ランジスタはパルス入力に対して急峻な立上り
および立下りを得られ、高速スイッチング動作を実現で
きる。As a result, the P-channel MO transistor (5) formed in the N-type well region (3) can obtain steep rises and falls in response to pulse input, and can realize high-speed switching operation.
また本発明はＮ型ウェル領域（３）を浅く形成するため
同一ドーズ量であれば従来の構造に比較してＮ型ウェル
領域（３）の表面不純物濃度を高く設定でき、フィール
ド反転電圧を従来のものより高くでき素子の信頼性を向
上できる。In addition, since the present invention forms the N-type well region (3) shallowly, the surface impurity concentration of the N-type well region (3) can be set higher than that of the conventional structure for the same dose amount, and the field reversal voltage can be set higher than that of the conventional structure. The reliability of the device can be improved.
（ト）発明の効果
本発明のＣＭＯＳ半導体装置の第１の効果は、Ｎ型ウェ
ル領域（３）を浅く形成することによりＰチャンネル間
Ｏ８）ランジスタのソースおよびドレイン領域（６）（
７）の接合容量を低減でき、高速動作に適するＣＭＯＳ
半導体装置を実現できる。(G) Effects of the Invention The first effect of the CMOS semiconductor device of the present invention is that by forming the N-type well region (3) shallowly, the source and drain regions (6) (
7) CMOS that can reduce junction capacitance and is suitable for high-speed operation
A semiconductor device can be realized.
本発明の第２の効果はＮ型ウェル領域（３）を浅く形成
することにより同一ドーズ量に対してその表面不純物濃
度を高く設定でき、フィールド反転電圧を胃くできＣＭ
ＯＳ半導体装置の信頼性を向上できる。The second effect of the present invention is that by forming the N-type well region (3) shallowly, the surface impurity concentration can be set high for the same dose, and the field reversal voltage can be reduced.
The reliability of the OS semiconductor device can be improved.
第１図は本発明に依るＣＭＯＳ半導体装置を説明する断
面図、第２図は従来のＣＭＯＳ半導体装置を説明する断
面図である。
主な図番の説明
（１）は半導体基板、 （２）はＰ型ウェル領域、（３
）はＮ型ウェル領域、 ｔ６）（７）はＰチャンネルＭ
ＯＳトランジスタのソースおよびドレイン領域、（１３
）（９）はゲート電極である。
出願人 三年電機株式会社 外１名
代理人 弁理士 佐 野 静 大
箱１図
第２図FIG. 1 is a sectional view illustrating a CMOS semiconductor device according to the present invention, and FIG. 2 is a sectional view illustrating a conventional CMOS semiconductor device. Explanation of the main figure numbers (1) is the semiconductor substrate, (2) is the P-type well region, (3
) is the N-type well region, t6) (7) is the P-channel M
Source and drain region of OS transistor, (13
)(9) is a gate electrode. Applicant Sannen Denki Co., Ltd. and one other representative Patent attorney Shizuka Sano Figure 1 Figure 2
Claims (1)
ル領域およびＮ型ウェル領域と該Ｐ型ウェル領域表面に
設けたＮチャンネルＭＯＳトランジスタと前記Ｎ型ウェ
ル領域表面に設けたＰチャンネルＭＯＳトランジスタと
を具備するＣＭＯＳ半導体装置に於いて、前記Ｎ型ウェ
ル領域を前記ＰチャンネルＭＯＳトランジスタのソース
およびドレイン領域より浅く形成することを特徴とした
ＣＭＯＳ半導体装置。(1) An N-type silicon substrate, a P-type well region provided on the surface of the substrate, an N-type well region, an N-channel MOS transistor provided on the surface of the P-type well region, and a P-channel MOS provided on the surface of the N-type well region. A CMOS semiconductor device comprising a transistor, wherein the N-type well region is formed shallower than the source and drain regions of the P-channel MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60007814A JPS61166155A (en) | 1985-01-18 | 1985-01-18 | Cmos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60007814A JPS61166155A (en) | 1985-01-18 | 1985-01-18 | Cmos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61166155A true JPS61166155A (en) | 1986-07-26 |
Family
ID=11676061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60007814A Pending JPS61166155A (en) | 1985-01-18 | 1985-01-18 | Cmos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61166155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01290253A (en) * | 1988-05-18 | 1989-11-22 | Sanyo Electric Co Ltd | N-well complementary semiconductor device and manufacture thereof |
| US6373106B2 (en) | 1996-09-10 | 2002-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
-
1985
- 1985-01-18 JP JP60007814A patent/JPS61166155A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01290253A (en) * | 1988-05-18 | 1989-11-22 | Sanyo Electric Co Ltd | N-well complementary semiconductor device and manufacture thereof |
| US6373106B2 (en) | 1996-09-10 | 2002-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
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