JPH01290253A - N-well complementary semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease a P-N junction in a junction capacitance of a source/ drain region of a P channel type MOS transistor and concurrently improve the P-N junction in a junction breakdown strength by a method wherein an N well is composed of a first well region of high impurity concentration and a second well low in impurity concentration. CONSTITUTION:A second well region 3 is selectively formed on the surface of a P-type semiconductor substrate 1, and a first well region 2 whose impurity concentration is higher than that of the second well region 3 is formed on the surface of the second well region 3. That is, an N well region consists of a surface part formed of the first well region 2 high in impurity concentration and the rest or an inner part formed of the second well region of low impurity concentration. Therefore, a source and a drain region, 14 and 15, of a P channel type MOS transistor 12 formed in the 11 well region and the second well region 3 form a P-N junction together. By these processes, the P-N junction formed of the source and the drain region, 14 and 15, can be decreased in a junction capacitance and also remarkably improved in a breakdown strength.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an N-well complementary semiconductor device and a method for manufacturing the same.

(B) Conventional technology In conventional complementary semiconductor devices, it is common to use a P-well, form a P-channel MOS transistor on the surface of an N-type substrate, and form an N-channel MOS transistor on the surface of the P-well. Met.

However, E
For FROM, RAM, COD, etc., forming an N-channel MOS transistor on a P-type semiconductor substrate and forming a Pf channel MOS transistor in the N-well region is advantageous for speeding up and makes it easier to disperse the substrate current. It had advantages. Therefore, such EFROM, RAM, COD
etc. adopted an N-well complementary semiconductor device.

A cross-sectional view of the structure of the N-well complementary semiconductor device will be described with reference to FIG. (21) is a P-type semiconductor substrate, (22)
is an N-well region, and (23) is a LOGO8 oxide film.

(24) is the Pf− formed on the surface of the N-well region (22).
It is a Jannel type MO3)-transistor with P+ type source/drain regions (25) (26) and a gate oxide film (2).
7) and a polysilicon gate electrode (28) provided thereon.
) is more fully formed. (29) is an N-channel MOS transistor formed on the surface of the substrate (21);
It is formed of type 4 source/drain regions (30, 31), a gate oxide film (32), and a polysilicon gate electrode (33) provided thereon.

In the above N-well complementary semiconductor device, the substrate (21)
Since phosphorus ions (11P+) are ion-implanted from the surface and formed by drive-in, the impurity profile shown in FIG. 4 is obtained. That is, the N-well region (22) has the highest impurity concentration at the surface, and has a Gaussian distribution along the depth direction of the substrate.

Note that such prior art includes Japanese Patent Application Laid-Open No. 60-35560 (HOIL 27108).

C) Problems to be Solved by the Invention In the conventional N-well complementary semiconductor device described above, since the N-well region (22) is formed later by ion implantation,
The surface impurity concentration of the well region (22) is 10"Cm-
', and P formed on the surface of the N well region (22)
A high impurity concentration PN junction is formed with the source/drain regions (25) and (26) of the channel type MOS transistor (24), increasing the junction capacitance.
There was a problem that the switching speed of the S transistor (24) was delayed.

Similarly, due to the high impurity concentration of the PN junction, the junction breakdown voltage also decreases, reaching a limit of about 25V, and the P-channel type M
Another problem was that it was difficult to increase the voltage resistance of the OS transistor (24).

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and the N-well region is divided into a first well region with a high impurity concentration in the surface portion and a second well region with a low impurity concentration in the remaining deep portion. By forming the semiconductor device in a well region, an N-well complementary semiconductor device and a method for manufacturing the same are realized which solve the problems of the conventional method.

(*) Effect According to the present invention, the N-well region is placed in the first region with high impurity concentration.
Since it is formed by a well region and a second well region with a low impurity concentration, a PN junction is formed between the source drain region of the P channel type MOS transistor formed in the N well region and the second well region with a low impurity concentration. do. As a result, the junction capacitance of the PN junction forming the source/drain region of the P-channel MOS transistor is reduced, and the withstand voltage can be significantly improved.

(F) Embodiment An embodiment of the present invention will be described in detail below with reference to FIGS. 1A to 1F.

As shown in FIG. 1A, a second well region (3) is selectively formed on the surface of a P-type semiconductor substrate (1). That is, the substrate (
1) After forming a thin pad oxide film (not shown) on the surface, the surface of the substrate (1) is covered with a resist layer (4) except over the intended N-well region. After that, using the resist layer (4) as a mask, phosphorus ions ("P") were applied at 160 keys.
Ion implantation was performed under the conditions of 2 x 10 "Cm-" (7), JJ1200℃TeO*'X ambient temperature 3 hours, N
.

Drive-in is performed in an atmosphere for 7 hours to form a second well region (3) with a depth of about 6 μm. Therefore, the second well region 3) has a low impurity concentration of about 1018 cm-3 or less.

Next, as shown in FIG. 1B, a first well region (2) having a higher impurity concentration is formed on the surface of the second well region (3). A resist layer (5) is again deposited on the surface of the substrate (1) through a pad oxide film (not shown) so as to expose the surface of the second well region (3), and this resist J'! (5) as a mask, phosphorus ion (31p-) at 160KeV,
Ion implantation is performed under the conditions of 3×10'1 cm-''.

In this step, in order to form the first well region (2) shallowly, only ion implantation is performed and no drive-in is performed.

Next, as shown in FIG.
A thick field oxide film (7) is formed by the LOCO3 method on the portion where . Since the LOCO8 method is well known, its explanation will be omitted, but a field oxide film with a thickness of approximately 8000 mm is embedded in the substrate (1) by thermal oxidation over the field region, leaving the active region (8) where the MOS transistor is formed. (7) is formed. Note that using this step, the first well region (2) formed in the previous step is driven in to form the first well region (2) with a depth of about 0.5 μm. The surface impurity concentration of the first well region (2) is about 101'cm-1, which is about an order of magnitude higher than that of the second well region (3).

Next, as shown in the first diagram, the gate electrode (1) of the complementary MOS transistor is placed on the gate oxide film (9) on the active region (8) on the substrate (1) and the first well region (2).
0) (11) is formed. In this process, reduced pressure CV is applied to the entire surface.
A polysilicon layer is deposited by method D, doped with phosphorus to a high impurity concentration, and then etched into a desired shape to form gate electrodes (10) and (11).

Next is the first one! As shown in ff1E, the first well region (2)
A P-channel type MOS transistor (12) is formed on the surface. The active region (8) of the substrate (1) is selectively covered with at least a resist layer (13), and source/drain regions (14) and (15) having an LDD structure are formed at a distance. Specifically, the gate electrode (10) and its vicinity are covered with a resist layer (not shown), and boron ions (I
IB4″) at 30 KeV, 2 X 10″cm
-" ion implantation to form P" type source/drain regions (14, 15) at least deeper than the first well region (2). Subsequently, this resist layer was removed, and using the gate electrode (10) as a mask, poron ions (IIB4'') were irradiated at 45KeV, 5X1 using self-line technology.
Ion implantation is performed under the condition of 0'1 cm-'' to shallowly form P- type source/drain regions (14, 15) adjacent to the gate electrode (10).

Furthermore, as shown in FIG. 1F, an N-channel MOS transistor (16) is formed on the surface of the substrate (1). The active region (8) of the first well region (2) is selectively covered with at least a resist layer (17), and the gate electrode (11) is
Using Selfaline technology as a mask, arsenic ions ("As") were implanted under the conditions of 80 KeV and 5 x 10 "cm-" to form N1 type source/drain regions (18).
(19) is formed.

In the N-well complementary semiconductor device formed through the manufacturing steps shown in FIGS. 1A to 1F described above, the first well region (
2) and the second well region (3) form an N-well, so a P-channel MOS transistor (12) formed in the N-well with an impurity profile as shown in FIG. 2 is as follows. Has characteristics. First, the P9 type source/drain regions (14) and (15) are placed in the second region with a low impurity concentration.
Since most of the PN junction is formed with the well region (3), the junction capacitance of the PN junction of the source/drain regions (14, 15) can be reduced to about 173 compared to the conventional structure. Further, due to the low impurity concentration PN junction, the junction breakdown voltage is greatly improved, and can be increased from about 25V in the conventional case to about 45V. Second, since the channel region is formed under the gate electrode (10) of the first well region (2), only the channel region can be made to have a high impurity concentration, and the short channel effect can be suppressed. Therefore, bunch-through in the channel region can be suppressed, and miniaturization of the P-channel MOS transistor by shortening the channel can be realized.

(G) Effects of the Invention As described above, in the present invention, by forming the N well with the first well region (2) with a high impurity concentration and the second well region (3) with a low impurity concentration, Channel type M
Source drain region (14) of oS transistor (12)
) (15) The junction capacitance of the PN junction can be reduced and the junction breakdown voltage can be significantly improved. As a result, PfJv tunnel type MO
It has the advantage that the switching speed of the S transistor (12) can be improved and a high breakdown voltage driver transistor for a fluorescent display tube (FLI') can be incorporated.

Further, since the channel region can be made to have a high impurity concentration in the first well region (2), short channel effects can be suppressed, devices can be miniaturized, and there are advantages that can contribute to improving the degree of integration.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views illustrating a method for manufacturing an N-well complementary semiconductor device according to the present invention, FIG. 2 is a curve diagram illustrating an impurity concentration profile of an N-well according to the present invention, and FIG. FIG. 3 is a cross-sectional view illustrating a conventional N-well complementary semiconductor device, and FIG. 4 is a curve diagram illustrating the impurity concentration profile of a conventional N-well. (1) is a P-type semiconductor substrate, (2) is a first well region, (
3) is the second well region, (4) and (5) are the resist layers, (
6) is the field region, (7> is the field oxide film, (
8) is the active region, (9) is the gate oxide film, (1
0) (11) is the gate electrode, (12) is the P-channel type MoS transistor, (14) (15) is the source/drain region, (16) is the N-channel type MOS transistor, (18) and (19) is the N0 type This is the source/drain region.

Claims (2)

[Claims] (1) A P-type semiconductor substrate, an N-type well region provided on the surface of the substrate, an N-channel MOS transistor provided on the surface of the substrate, and a P-channel MOS transistor provided in the well region
An N-well complementary semiconductor device having an OS transistor, characterized in that the N-type well region is formed by a first well region having a high impurity concentration in a surface portion and a second well region having a low impurity concentration in the other portion. N-well complementary semiconductor device. (2) Forming a second well region by ion-implanting and driving in N-type impurities into a desired region of the P-type semiconductor substrate, and forming an impurity by ion-implanting N-type impurities into the surface of the second well region. a step of forming a first well region with a high concentration; a step of forming a field oxide film on a portion of the substrate and the first well region that will become a field portion;
A method for manufacturing an N-well complementary semiconductor device, comprising the steps of forming a P-channel MOS transistor in the first well region and forming an N-channel MOS transistor in the substrate.