JPS6057661A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance of the titled semiconductor device, to prevent the short channel effect generating thereon as well as to contrive accomplishment of high speed operation of a CMOS device by a method wherein high density impurity layers of the same type are selectively formed on a low impurity density substrate and a well on the region located in the vicinity of a source and drain and a channel only. CONSTITUTION:An Si3N4 mask 21 is formed on the SiO2 film 20 located on a P<-> type Si substrate 1, As and P are implanted 23, and an N<-> well 2 and an N-layer 5 are simultaneously formed by performing a thermal diffusion. B is implanted 24 using the SiO2 25 obtained when the above-mentioned process is performed, a P-layer 4 is formed by performing a thermal diffusion, and after the above has been selectively insulation-isolated 3, gate oxide films 10 and 11 are coated thereon. Subsequently, an N-ch type IGFET is formed as usual on the P-layer 4 and a P-ch type IGFET is formed on the N-layer 5. When the layer 4 and 5 are formed in the thickness wherein the depletion layer on the lower part of each source can reach the substrate or the well penetrating the layers 4 and 5 and the impurity density with which a punch- through is not generated on a channel is selected, a short-channel effect can be prevented by the reduction of expansion of the depletion layer on the channel, and the junction capacitance of the source and the substrate can be reduced because the depletion layer expands easily on the region other than the channel, thereby enabling to perform a high speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to increasing the speed of a complementary MO8 semiconductor device.

[Background technology]

Complementary MO8 semiconductor device
Metal Oxicle Sem1conducto
r: hereinafter referred to as CMO8) is being developed in the direction of speeding up.

In order to increase the speed of a semiconductor device, the time constant within the semiconductor device, which is the product of resistance and capacitance, can be reduced. Specifically, various things are required, such as reducing the junction capacitance between the source/drain and the surrounding region, such as a well layer or substrate, and reducing wiring resistance.

The junction capacitance between the source/drain layer and the well layer or substrate is
It is determined by the extent of the depletion layer formed around the source layer. As for the junction capacitance between the source/drain layer and the substrate, the larger the spread of the formed depletion layer, the smaller the junction capacitance becomes. Conversely, the smaller the depletion layer is, the larger the junction capacitance becomes. Therefore, in order to achieve high speed, it is necessary to widen the depletion layer as much as possible. The extension of the depletion layer around the source layer, which determines the junction capacitance, is
It is determined by the impurity concentration of the well layer surrounding the source region and the substrate. If the impurity concentration of the well layer or substrate is high, the depletion layer will not extend as much, and if the impurity concentration is low,
A large depletion layer is formed. Therefore, in order to increase the speed, it is necessary to form a layer around the source diffusion layer, that is, a substrate or a well layer, to have a low impurity concentration.

However, if the impurity concentration of the substrate (or the impurity concentration of the well layer) is formed at a low concentration in order to increase speed, a depletion layer will also be formed extensively in the channel region, and the channel width, which should be determined by the gate width, will be reduced. The length will be inconsistent. This phenomenon is called the short channel effect. Especially when the gate length is shortened, the source
Punch-through occurs between drains. In order to prevent such short channel effects, it is necessary to reduce the concentration of the layers surrounding the source/drain layer, contrary to the technique described above that reduces the concentration of the layers surrounding the source/drain layer, such as the well layer or the substrate. It is necessary to make the depletion layer formed in the channel region as small as possible.

As mentioned above, contradictory problems have become known as speed increases; for example, Nikkei Electronics 1988
It is written in the June 21, 2016 issue, etc.

In order to achieve high speed, it is necessary to solve the above problems.

Furthermore, the above-mentioned problems also apply to MO8iC in general.

[Purpose of the invention]

A first object of the present invention is to provide a technique for sufficiently reducing the junction capacitance between a source/drain diffusion layer and a substrate.

A second object of the present invention is to provide a technique for preventing short channel effects.

A third object of the present invention is to provide a technique for increasing the speed of a semiconductor device by simultaneously achieving the first and second objects.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

゛ That is, the substrate and the well layer of CMO8 are formed as semiconductor layers having a low impurity concentration, and further,
A semiconductor impurity layer of the same type having a higher impurity concentration than the substrate or well layer is present only in the vicinity of the source/drain layer and in the channel region. This impurity layer is
The depletion layer formed under the source layer escapes from this impurity layer and reaches the substrate or well layer, and the impurity concentration of the impurity layer is as follows:
The concentration is such that punch-through does not occur in the channel region. Because of this impurity layer formation,
The spread of the depletion layer formed in the channel region is reduced,
The short channel effect almost disappears. moreover,
The depletion layer formed in a region other than the channel region escapes from this impurity layer and extends sufficiently into the well layer or substrate region, so that the junction capacitance between the source region and the substrate becomes small and high speed can be achieved.

〔Example〕

FIG. 1 is a sectional view of a CMO8 semiconductor device to which the present invention is applied, and FIG. 2 is a CM having the sectional view of FIG. 1 along line A-A.
The plan view of the O8 semiconductor device, FIGS. 3 to 8, are cross-sectional views taken along line A-A' in FIG. 2, showing the manufacturing process of the present invention.

In FIGS. 1 and 2, an N-channel type insulated gate field effect transistor (hereinafter referred to as MISFET) Ql and a P-channel type MISI"ETQ2 are connected to a field insulating film made of silicon oxide (Sin). 3.LllL, is MISFET
This is an active region where Q+ and Qz exist, and through a gate 12 that runs across FIG.
A north drain diffusion layer is present. An input signal is input to the gate 12 made of polycrystalline silicon, and an output signal is output to the wiring 18 through drain diffusions R7 and R8. There is a contact hole in the active region (L2)! Aluminum wirings 17 and 19 for supplying power supply voltage are in ohmic contact with the source diffusion layers 6 and 9 through contact holes H, H4. The aluminum wire 18, which is involved in the output signal, makes ohmic contact with the drain diffusion layer 7.8 of each of the MISFETs Q+ and Q through contact holes H2 and H3.

The configuration of the present invention will be explained in more detail as follows. An N-type well layer 2 for forming MISFET Q2 is formed on a P-type semiconductor substrate. active area L
As described above, in the active region L2, the N+ type scattering layer 67 for forming the source/drain is provided, and in the active region L2, the N- type scattering layer 67 is provided.
In the type well layer 2, there is P for forming source/drain.
A type diffusion layer 8.9 is present. A thick field insulating film 3 made of silicon oxide (si02) exists between these two active regions to insulate each MISFET. Furthermore, silicon oxide (S) is formed on the active region.
A gate insulating film 10.11 made of iO□) is present, and a gate 12 made of polycrystalline silicon is present thereon. The gate 12 made of polycrystalline silicon has a silicon oxide film 13 formed on its surface to prevent electric field concentration at the edge.

The feature of the present invention is that, as shown in FIG. It's about doing. Now, if we shift our attention only to MISFBTQ, MISF
P around the N++ source/drain layer 6.7 of BTQ.
Type impurity Fi4 is formed. This P-type impurity layer 4
has a higher impurity concentration than the P-type semiconductor substrate 1, and the MIS
It covers the channel region of the I''ETQI to a depth similar to that of the source/drain layer, and is present so as to shallowly surround the lower part of the source/drain layer. In this case, the depletion layer is formed to a depth such that it escapes from the P-type impurity layer 4 and extends into the substrate, and its concentration is such that the depletion layer does not extend and punch-through occurs in the channel region. , in the channel region, the MISFET
Q. The formation region of the depletion layer formed around the source layer 6 during operation becomes small, and short channel effects due to the depletion layer in the channel region rarely occur.

In addition, the high concentration P-type diffusion layer 4 formed in the present invention is formed only shallowly near the bottom of the source/drain layers 6 and 7, so the depletion layer extending below the source layer 6 is a P-type diffusion layer 4. Leaving the type impurity layer 4, the P- type semiconductor substrate 1
The formation region is wide below the source layer 6. Therefore, the junction capacitance between the source/drain layer 6 and the substrate 1 becomes small due to the expansion of the depletion layer within the N- type semiconductor. As described above, the presence of the P-type impurity layer 4 around the source/drain layers in the present invention simultaneously reduces the short channel effect and the junction capacitance between the source/drain layers 6, 7 and the substrate 1. is possible.

M I 8 B' E formed on the N-well layer
The same can be said for TQ2. Tsukali, MIS
An N-type impurity layer 5 is formed around the P-type source/drain diffusion layer 8.9 of the FBTQ2. The N-type impurity layer 5 is
Higher than the impurity concentration of N-type well layer 2, MISFB
It covers the channel region of TQ2 to a depth of approximately the depth of the source/drain layers 8, 9, and is present so as to shallowly surround the lower portions of the source/drain layers 8, 9. MISI”ETQ
When operating MISFETQ2, the principle works almost the same as when operating MISFETQ+, and the short channel effect in MISFBTQ2 is reduced, and the source/drain layer 8.
It is possible to reduce the junction capacitance between the N-type well layer 9 and the N-type well layer 2 at the same time.

In FIG. 1, reference numeral 16 indicates a first glass plate made of phosphosilicate glass (PSG) formed to protect the device.
It is a passivation film, and 16 is a phosphosilicate glass (PSG) which is also provided to protect the element.
Final passivation consisting of films, etc. Jlif, S
Ru.

Hereinafter, the manufacturing process of the present invention will be explained using FIGS. 3 to 8.

First, a P-type single crystal silicon substrate 1 having a (100) crystal plane is prepared. A silicon oxide (SiO2) film 20 is formed on the surface of this silicon substrate 1 by thermal oxidation as shown in FIG. This silicon oxide (Sin2) film 20
is a protective film for protecting the substrate during ion implantation for forming the N-type well layer 2 shown in FIG. N-
In order to form the type well layer 2, a silicon nitride (SI3N4) film 21 is selectively formed using a 7-layer photoresist film 22 in a region other than the area where the N-type well layer 2 is to be formed, as shown in FIG. In order to form the N-type well layer 2 shown in FIG. - type semiconductor substrate 1 in Fig. 3, 23
Type as shown. After implanting arsenic (A, s) and phosphorous (t), arsenic (A, A s ) and phosphorus (1
') to diffuse. P of arsenic (A s ) and phosphorus (T)
Since the diffusion rates into the − type semiconductor substrate are different, it is possible to form the N − type well layer 2 and the N type impurity layer 5 of the present invention at the same time by one thermal diffusion. The structure formed in this manner is shown in FIG. The N-type impurity layer is formed for reasons other than becoming an active region later on, but it also serves as a channel stopper under the field insulating film.

Since thermal diffusion is performed without removing silicon nitride H(S13N4) 2 i, the slightly thick silicon oxide film 25 becomes N-
A type well is formed over the diffusion region. MI shown in Figure 1
In order to form the P-type diffusion region 4 of S F E T Q + , a P-type impurity, such as boron (C), is added by tJ using the thick silicon oxide film 25 formed on the N-type well diffusion region as a mask. A P-type impurity implantation layer 24 is formed as shown in FIG. As is obvious,
By forming a somewhat thick silicon oxide (Sin2) film 25, it is possible to implant P-type impurities in a consistent manner. As shown in FIG. 4, after forming an N-type well layer 2 and an N-type impurity layer 5, P
Thermal diffusion is performed to diffuse type impurities into the semiconductor substrate 1, and all silicon oxides [20, 25 formed on the substrate are removed (not shown). This P-type impurity also serves as an impurity layer covering the source/drain layer, which is the key point of the present invention, but also serves as a channel stopper under the field insulating layer.

As described above, the N-type well layer 2. N-type impurity layer 5. After forming the P-type impurity layer 4, a thin silicon oxide film (not shown) is formed on the entire surface of the silicon substrate to form a field insulating film. A silicon nitride (SisN4) film (not shown) is selectively formed using a photoresist film (referred to as a CVD method). Using this silicon nitride film (not shown) as a mask, the surface of the silicon substrate is thermally oxidized.
A thick field insulating film 3 consisting of in, ) is formed.

This is an insulating film for insulating adjacent M I S F E '1'. Furthermore, the thin silicon oxide film (not shown) and silicon nitride film (not shown) formed on the silicon substrate used for forming the field insulating film 3 are removed, and a thin gate insulating film made of silicon oxide (Sin2) is removed. Membranes 10.11 are formed as shown in FIG. When forming this thin insulating film 10°11, in order to obtain purity, the silicon substrate is first thermally oxidized to remove the thin oxide film formed on the surface (m), and then formed. The prepared silicon oxide (SiO2) JIJ is a silicon substrate 1
This serves as the gate insulating film for all M:l5Ii"ETs formed in the process.

Next, a polycrystalline silicon film for forming a gate is formed on the entire surface of the gate insulating film 10.11 and the field insulating film 3 by using, for example, the CVD method. Furthermore, in order to make the polycrystalline silicon layer conductive,
An impurity, such as phosphorus (Pit ion implantation method) is introduced into the polycrystalline silicon layer. Then, a photoresist film (not shown) is selected to remove the polycrystalline silicon layer in areas other than the area where the gate is to be formed. Then, using this photoresist film as a mask, a polycrystalline silicon layer 12 is formed.Furthermore, in order to form a source/drain layer, a polycrystalline silicon layer 12 is formed to form a gate.
2 as a mask, desired impurities are introduced into the source/drain regions. First, for example, a silicon oxide (S1O2) film 26 is formed over the entire surface in a high-temperature, low-pressure atmosphere, and then a silicon oxide (S1O2) film 26 is formed in areas other than the N-type well layer where the P-type source/drain layer will be formed. is formed using a photoresist film (not shown) as shown in FIG. Using this silicon oxide (Sin2) film 26 as a mask, N2! ! ! An N-type impurity, such as phosphorus (F5), is implanted into the source/drain region of the MISFET, which is to have a source/drain layer, through the silicon oxide film 10'1r on the source/drain region. The N-type impurity introduced into the region is thermally diffused to form source/drain layers, thereby forming desired source/drain layers.

After the treatment, the element surface is cleaned and a polycrystalline silicon layer 12
0 surface is lightly oxidized to form a thin silicon oxide film 13.

(other than 16M I S li' ET) on the well layer
After forming the source and drain layers of M I S II''ET as described above, the silicon oxide (Si02) film 26 on the N-type well layer 2 is removed, and the silicon oxide (Si02) film 26 on the N-type well layer 2 is formed in the same manner. MISFET, for example MISFETQt
Form source/drain layers. For example, similarly N
- M I S F E T other than on the mold wafer/I/layer
, /ξ For example, a region where MISFETQ exists is selectively covered with a silicon oxide film formed in a high temperature and low pressure atmosphere, and a P type impurity, such as boron (I9), is introduced into the N- type well layer. The introduced P type impurity is thermally diffused to form P+ type source/drain layers 8 and 9 within the N- type well layer. A silicon oxide film 13 is formed.The shape formed as described above is shown in FIG.

After forming the device as described above, the first pansivation film is formed using a well-known method, the aluminum (i) wiring is formed in a desired pattern, and the final passivation is performed.
Li1-formation fl.

That is, a phosphosilicate glass (PSG) film is provided over the entire surface by, for example, the CVD method, and necessary contact holes such as N, H2, H3, and H are formed to form a first passivation film. Furthermore, as shown in FIGS. 8 and 2, aluminum (A7) wirings 17, 18, and 19 relating to input/output signals, power supply voltage, etc. are formed.

Finally, as shown in FIG. 1, a final passivation film is formed using, for example, phosphosilicate glass (PSG).

〔effect〕

(1) Impurity layers 4 and 5 of a conductivity type opposite to that of the source/drain exist around the source/drain layer. The diffusion layers 4 and 5 are formed at a higher impurity concentration than the semiconductor substrate or well layer on which the MISFET is formed, and cover the channel region of the MISFET to a depth comparable to the source/drain layer. - Since the impurity regions 4 and 5 are formed so as to shallowly encircle the lower part of the drain layer, the impurity regions 4 and 5 are formed only shallowly in the vicinity of the lower part of the source/drain layer.

Not yet. Therefore, the depletion layer extending below the source layer escapes from the formed impurity region and extends into the semiconductor substrate with a low impurity concentration or within the well layer, and the region is formed to be wide. Therefore, the junction capacitance between the source/drain layer and the substrate becomes small due to the large spread of the depletion layer.

(2) In the channel region, since there are impurity layers 4 and 5 with higher concentration than the substrate or well layer, MIS
The formation region of the depletion layer formed around the source layer during FET operation becomes small, and the short channel effect due to the depletion layer in the channel region hardly occurs. Therefore, a desired channel length can be obtained.

(3) Due to the effects (1) and (2) above, the speed of the semiconductor device can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the present invention, the well layer 2 is an N-type conductive layer, but the well layer 2 is a P-type conductive layer, and the substrate is an N-type conductive layer.
Even if a type semiconductor substrate is used, the effects of the present invention are not impaired. In this case, the impurity layers 4 and 5 of the present invention become an N-type impurity layer and a P-type impurity layer, respectively, and the N-type impurity layers shown in FIG.
The + type source/drain layers 6, 7 become P type source/drain layers, and the P+ type source/drain layers 8, 9 become N+ type source/drain layers.
This becomes the type drain layer. Furthermore, although a phosphosilicate glass (PSG) film is used as the first passivation film, it may be formed of silicon oxide or the like, and the final passivation film may be formed of a plasma film or the like. Furthermore, the gate and, although not shown in this embodiment, the source and drain
It goes without saying that the effects of the present invention will not be impaired even if the FL pole is made of a high melting point metal such as platinum or molybdenum, or silicide. Furthermore, the same effect can be obtained even if only one of the impurity layers 4 and 5 of the present invention is removed.

[Field for U]

In the above explanation, the invention made by the present inventor was mainly applied to the technology of CMO8 semiconductor device, which is the background field of application.
It is possible to apply the present invention not only to semiconductor devices formed using only one of the channel MOS li' ETs, but also to MO8 semiconductor mounting in general.

[Brief explanation of drawings]

1 is a sectional view of a CMO8 semiconductor device to which the present invention is applied; FIG. 2 is a plan view of a CMO8 semiconductor device having the sectional view of FIG. 1 taken along line A-h'; Figure 8 shows h in Figure 2 showing the manufacturing process of the present invention.
- It is a sectional view along the i line. l...P-type semiconductor substrate, 2...N-type well layer,
3... Field insulating film made of silicon oxide (Sio), 4... P-type impurity layer of the present invention, 5... N-type impurity layer of the present invention, 6... N'''' type source layer, 7.
...N+ type drain layer, 8...P type train layer, 9
... P+ type source layer, 10.11... Kate insulating film made of silicon oxide (SiC) +), 12... Gate electrode made of polycrystalline silicon, 13... Oxidation that holds the gate electrode Silicon film, 14... Final passivation film consisting of phosphosilicate glass (I) &J-, 15... Silicon oxide film, 16.
. . . The first banyan layer made of phosphosilicate glass (PSG) M [, 17, 18, 19 . . . Aluminum (At) wiring layer, 20 .
2) IIK, 21...silico nitride y (8i s N
4) Membrane, 22-GjFJki'flQ, 23°24...
・Phosphorus (P) and arsenic (As) implanted layer, 25...
・Silicon oxide (Sin) layer, 26...Silicon oxide film, 27...Boron ■implantation layer, Q,,Q,...
・MISFET, L+, Lt...Active region, H,, H! ,H,,H. . . . Contact hole, C, , C, . . . Channel region. Figure 1 Figure 2 Figure 3/Figure 4

Claims (1)

[Claims] 1. A first region of a first conductivity type, a source/drain layer which is a second region of a second conductivity type formed in the first region of the first conductivity type, and a source/drain layer formed in the first region of the first conductivity type. The impurity concentration of the first conductor formed around the drain layer and in the channel region between the source and drain layers is higher than the impurity concentration of the first region and controlled to such an extent that punch-through does not occur in the channel region. and a third region in which an existing region is defined such that a depletion layer generated at the bottom of the source/drain layer reaches the first region. 2. A complementary MO8 semiconductor device in which the first region has a substrate or a well layer, and the third region exists in at least one of an active region existing on the substrate or an active region existing in the well layer. A semiconductor device according to claim 1, characterized in that: