JPH0279464A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide possibility of forming an alignment mark for photo-lithography without forming a level difference at the boundary of a well layer by allowing the main surface of first and second electroconductive type semiconductor regions to exist at the same level. CONSTITUTION:After an insulation film 17a is formed over the whole surface of a silicon base board, a polysilicon film 15 is deposited on it, and further thereon a resist film 14 in specified pattern is formed. Then etching is performed with this resist film 14 as a mask, and with a certain space reserved between, a word line 20 in a single piece with gate electrode and a gate insulation film 17 are formed in the P-type well layer 2 region of a memory cell forming region. In this etching process, no level difference part will be formed in the boundary region between the P-type well layer 2 and N-type well layer 3, nor any residues of polysilicon film and insulation film be generated in the boundary region. This accomplishes a CMOS type DRAM having capacitor of memory cell in a trench.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and particularly relates to a semiconductor memory device in which semiconductor regions of two different conductivity types are formed on a semiconductor substrate and a method for manufacturing the same. It is something.

[Prior Art] The most favorable effect can be obtained when this invention is applied to a CMOS dynamic random access memory (hereinafter referred to as DRAM).
-DRAM will be explained.

DRAM is already well known. FIG. 3 is a block diagram showing an example of the entire conventional DRAM (1M configuration).

Referring to FIG. 3, a DRAM includes a memory cell array 100 including a plurality of memory cells as a storage portion, a row decoder 2001 connected to an address buffer that selects the address, a column decoder 300 connected to an input/output circuit. and an input/output interface section including a sense amplifier. A plurality of memory cells serving as a storage portion are arranged in a matrix consisting of a plurality of rows and a plurality of columns. Each memory cell is connected to a corresponding word line connected to row decoder 200 and a corresponding bit line connected to column decoder 300, thereby forming memory cell array 100. A row decoder 200 and a column decoder 30 receive externally applied row address signals and column address signals.
A memory cell is selected by each word line and bit line selected by 0. Data 1 is written into the selected memory cell, or data stored in the selected memory cell is read out. This data read/write instruction is performed by a read/write control signal applied to the control circuit.

Data is N (-nXm) bit memory cell array 10
Accumulated to 0. Address information regarding memory cells to be read/written is stored in row and column address buffers, and the row decoder 200 selects a specific word line (selection of one word line out of zero). ), m-bit memory cells are coupled to the sense amplifier via bit lines. Next, column decoder 300
By selecting a specific bit t:me (selection of ] bit lines out of m focus lines), one of the sense amplifiers is coupled to the input/output circuit and read out according to the command of the control circuit. , or writing is delayed.

FIG. 4 is an equivalent circuit diagram of one memory cell 10 of a DRAM shown for explaining write/read operations of the memory cell. According to this figure, one memory cell 10 consists of a pair of field effect transistor Q and capacitor Cs. The gate electrode of the field effect transistor Q is connected to the word line 20, one source/drain electrode is connected to one electrode of the capacitor Cs, and the other source/drain electrode is connected to one electrode of the capacitor Cs.
The drain electrode is connected to the bit line 30.

At the time of data writing, a predetermined voltage is applied to the word line 20, so that the voltage boosting transistor Q becomes conductive, so that the charge applied to the bit line 30 is stored in the capacitor Cs. On the other hand, when reading data,
When a predetermined voltage is applied to the word line 20, the field effect transistor Q becomes conductive, so that the capacitor C
The charge stored in s is taken out via the bit line 30.

FIG. 5A is a plan view showing a wafer on which DRAMs configured as described above are fabricated as multiple semiconductor chips. Referring to FIG. 5A, each DRAM is formed as one chip 500, and a large number of chips 500 are fabricated one by one in a wafer 1000. 5th A
The portion VB in the figure is shown in FIG. 5B.

FIG. 5B is a partial plan view showing the boundary area between each chip within the wafer. According to this figure, each chip 500 is separated by a dicing line 600 as a region to be finally cut. chip 50
In the region 0, there is a P-type well layer 2, which is the region in which the memory cell array is to be built, and an N-type well layer 6 (region 1), in which the other parts constituting the peripheral circuits and the like are to be built. In other words, in this example, it is composed of a CMOS type DRAM.

In the area of the dicing line 600, an alignment mark 21 for aligning a photolithography mask used for patterning inside each chip 500 is provided.
is formed.

The manufacturing process along the cross section taken along the line Vl--Vl in Fig. 5B is shown in Figs. 6A to 6L or Figs. 7A to 7■.

FIGS. 6A to 6L are partial cross-sectional views showing, in order of steps, a method of manufacturing a CMO 8' JADRAM in which capacitors of memory cells are placed in trenches.

First, referring to FIG. 6A, an underlying oxide film 12 is formed on a P-type silicon substrate 1 by a thermal oxidation method or the like. A nitride film 13 is formed on the underlying oxide film 12 by a chemical vapor deposition method or the like.

Next, referring to FIG. 6B, after a resist film 14 is formed on nitride film 13, underlying oxide film 12, nitride film 13, and resist film 14 are selectively removed according to a predetermined pattern. Ru. At this time, in the region of the dicing line 600, the buried oxide film 12, nitride film 13, and resist film 14 are selectively removed according to a pattern for forming alignment marks. Using these patterned films as a mask, N-type impurity ions such as phosphorus ions or arsenic ions are applied in the direction indicated by the arrow.
It is implanted onto the P-type silicon substrate 1 at an accelerating voltage of 0 ke V.

Further, referring to FIG. 6C, after the resist film 14 is removed, thermal oxidation is performed. As a result, a thick oxide film 12a is formed on the top of the ion-implanted P-type silicon substrate 1.
is formed, and the implanted N-type impurity ions are diffused into the region below, thereby forming an N-type impurity diffusion region 3a.
is formed.

At the same time, in the region of the dicing line 600, a thick oxide film 12a is similarly formed by thermally oxidizing the exposed portion between the films patterned to form alignment marks.

Then, referring to FIG. 6D, after the nitride film 13 is removed, 10 to 20 P-type impurity ions such as boron ions are injected in the direction indicated by the arrow using the thick oxide film 12a as a mask.
It is implanted onto the P-type silicon substrate 1 at an accelerating voltage of about 01c e V.

As shown in FIG. 6E, the underlying oxide film 12 and the thick oxide film 12a are removed by dry etching or the like. Thereafter, the P-type silicon substrate 1 is subjected to heat treatment, so that the implanted N-type impurity ions and P-type impurity ions are thermally diffused. As a result, a P-type well layer 2 and an N-type well layer 3 are formed in the P-type silicon substrate 1.

Furthermore, within the region of the dicing line 600, an alignment mark 21 consisting of a recess formed by removing the thick oxide film 12a is created.

Then, as shown in FIG. 6F, P! ! Well layer 2 and N
A P-type impurity diffusion region 5 is formed as an inversion prevention layer at the boundary with the type well layer 3, and an isolation field oxide film 4 is formed thereon. Although not shown, a field oxide film for isolating between memory cells and a field oxide film for isolating elements such as transistors are also formed at the same time.

Referring to FIG. 6G, a trench is formed in P-type well layer 2 as a memory cell formation region.

At the bottom of the trench, a P-type impurity diffusion region 5 is formed as an inversion prevention layer by ion implantation or the like. This P
A thick isolation oxide film 4 for element isolation is formed on the yfJ impurity diffusion region 5. Furthermore, the trench groove Tr
After an N-type impurity diffusion region 6, which will become one electrode of the capacitor, is formed on the side wall of the capacitor by ion implantation or the like, a capacitor dielectric film 11 is formed by thermal oxidation, chemical vapor deposition, or the like. It is formed. Capacitor dielectric film 1
A polysilicon material containing conductive impurities such as phosphorus and arsenic is deposited on top of 1 by a method such as chemical vapor deposition, and then selectively removed.
Cell plate 9, ie, the other electrode of the capacitor, is formed.

As shown in Figure 6H, an oxide film, an electrode material such as a polysilicon material, or a composite structure thereof, such as a multilayer structure of a relatively thin oxide film and an electrode material, is formed on the entire surface of the silicon substrate. , a buried deposited layer 16a is formed.

Thereafter, referring to FIG. 61, buried deposited layer 16a is removed by etch-back so as to fill only the inside of the trench. At this time, when the buried deposited layer 16a is removed so that the buried deposited layer 16a fills the inside of the trench and is flattened against the silicon substrate, the gap between the P-type well layer 2 and the N-type well layer 3 is removed. Residues 22a of the buried deposited layer may be generated in the stepped portion formed at the boundary. If this residue 22a is removed by overetching, the buried isolation layer 16 filling the trench will also be removed. Problems when the residue 22a is generated in this step will be described later.

next,? As shown in Figure S6J, after an insulating film 17a is formed on the entire surface of a silicon substrate by a method such as a thermal oxidation method, a polysilicon film 15 is formed thereon. Furthermore, resist films 14 are formed on this polysilicon film 15 at selective intervals according to a predetermined pattern.

Sixth, referring to the figure, etching is performed using the resist film 14 as a mask, so that the gate insulating film 17 and the word line 20 formed integrally with the gate electrode formed thereon are spaced apart from each other. It is formed. In this etching step, a residue 22b of polysilicon film or the like is formed on the stepped portion formed at the boundary between the P-type well layer 2 and the N-type well layer 3.
may occur. If over-etching is performed to remove this residue 22b, the side wall surface of the word line 20 may be etched or the silicon substrate may be damaged as shown by the two-dot chain line.

Finally, as shown in FIG. 6L, an N-channel MOS transistor is formed in the region of P-type well layer 2 so as to be connected to the capacitor formed in the trench. This N-channel MOS transistor is composed of a word line 20 as a gate electrode and N-type impurity diffusion regions 61 and 62 as drain or source regions. One N-type impurity diffusion region 62 constituting the MOS transistor is connected via a contact hole C to a bit line 30 made of an aluminum layer or the like formed on an interlayer insulating film 18 made of a silicon oxide film. On the other hand, in the area other than the memory cell formation area, N! ! In the region of the well layer 3, a P-channel MO3I-transistor forming a peripheral circuit and the like is formed.

This P-channel MO3I-transistor is composed of a gate electrode 7 and P-type impurity diffusion regions 51 and 52 serving as source/drain regions in the N-type well layer 3.

In this way, a CMO3 type DRAM having a memory cell capacitor in the trench is formed.

7A to 7-7 are partial cross-sectional views showing, in order of steps, a method of manufacturing a CMO5 type DRAM in which the capacitor of the memory cell is a stacked capacitor.

First, with reference to FIGS. 7A to 7E, the P-type well layer 2
The process of forming the N-type well layer 3 and the N-type well layer 3 in the P-type silicon substrate 1 and forming the alignment mark 21 in the region of the dicing line 600 involves forming the memory cell in the trench shown in FIGS. CMO with capacitor
Since the manufacturing process is the same as that of the 9-inch DRAM, the explanation thereof will be omitted.

Next, referring to FIG. 7F, P! ! ! A P-type impurity diffusion region 5 as an anti-inversion layer is formed at the boundary between the well layer 2 and the N-type well layer 3 and in the element isolation region, and an isolation field oxide film 41 and 42 is formed thereon. .

As shown in FIG. 7C, after an insulating film 17a is formed on the entire surface of the silicon substrate by a method such as a thermal oxidation method, a polysilicon film 15 is deposited thereon.

Further, on the polysilicon film 15, an insulating film 17b7<
Deposited. A resist film 14 is formed on the insulating film 17b according to a predetermined pattern.

Referring to FIG. 7H, by etching the insulating film 17b1, the polysilicon film 15, and the insulating film 17a using the resist film]4 as a mask, the word line 20 sandwiched by the gate insulating film 17 is formed as a memory cell formation region. It is formed in the region of the P-type well layer 2. In addition, the N-type well layer 3
Similarly, a gate electrode 7 sandwiched between insulating films is formed in the region. In this etching step, residues 22b of the insulating film and polysilicon film may be generated at the step portion formed at the boundary between the P-type well layer 2 and the N-type well layer 3. If overetching is performed to remove this residue 22b, the side walls of the word vA20 and the gate electrode 7 will be etched, and the silicon substrate will be damaged as shown by the two-dot chain line.

Problems that occur when this residue 22b is generated will be described later.

Finally, as shown in FIG. 7, an N-channel MOS transistor and a stacked capacitor constituting each memory cell are formed in the region of the P-type well layer 2. This N
The channel MOS transistor is composed of a word line 20 as a gate electrode and N-type impurity diffusion regions 61 and 62 as a drain or source region. Also, this N
Channel MOS1 - Stacked connected to transistor
The capacitor is connected to one N-type impurity diffusion region 61 and is formed of a storage node 8 which serves as one electrode formed of a conductive layer such as polysilicon, and a similar conductive layer extending above the storage node 8. A capacitor dielectric film 1 made of a nitride film or the like sandwiched between a cell plate serving as the other electrode, a straight node 8 and a cell plate 9.
1. The other N-type impurity diffusion region 62 constituting the N-channel MOS transistor is connected via a contact hole C to a bit line 30 made of an aluminum layer or the like formed on an interlayer insulating film 18 made of a silicon oxide film. be done. On the other hand, in a region other than the memory cell formation region, a P-channel MOS transistor constituting a peripheral circuit etc. is formed in the region of N-type well layer 3. This P-channel MOS l-transistor is composed of a gate electrode 7 and P-type impurity diffusion regions 51 and 52 serving as source/drain regions in the N-type well layer 3.

In this way, CM with stacked capacitors
An OS type DRAM is formed.

As mentioned above, two examples of the CMO3 type DRAM have been shown, but there are other examples of using the stepped portion formed in the boundary region of the well layer as an alignment mark for mask alignment for photolithography, for example, in the US patent. No. 4,443.811.

[Problems to be Solved by the Invention] In the above-described conventional CMOS type DRAM, a stepped portion is formed in the boundary region of the well layer. Therefore, as shown in FIG. 61, residue may be generated at the boundary of the well layer during the process of burying the trench. Also, the 6th
As shown in Figure 1 or Figure 7H, for example, when forming conductive layer parts at intervals such as gate electrodes by etching, residues are generated at the boundaries of the well layer during the etching process. There are cases.

Such residue remains at the boundary of the well layer,
When a DRAM is manufactured by performing post-process processing, there is a problem in that electrical short circuits and the like occur due to the residual portions. Furthermore, if over-etching is performed to remove the residual portion shown in Figure 6, it becomes impossible to completely fill the trench, resulting in an electrical short circuit with the wiring layer formed above. There was a problem with that. Furthermore, if over-etching is performed to remove the residue shown in Figures 6 and 7H, the side walls of the conductive layer such as the gate electrode will be etched, or the silicon substrate will be etched. Since damage is caused, there is a problem in that the performance of the transistor is deteriorated.

Therefore, the present invention was made to solve the above-mentioned problems, and provides a semiconductor memory device in which alignment marks for photolithography can be formed without forming steps at the boundaries of well layers. Our aim is to provide a method for producing the same.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a semiconductor substrate and a second conductivity type semiconductor region.

The semiconductor substrate has a main surface and is of a first conductivity type.

A second conductivity type semiconductor region is formed in this semiconductor substrate. Thereby, the first semiconductor region of the first conductivity type;
The semiconductor substrate is divided into a second conductivity type second semiconductor region having a main surface on the same level as the main surface of the first semiconductor region.

According to the method of manufacturing a semiconductor memory device according to the present invention,
First, a first conductivity type semiconductor substrate having a main surface is prepared. Patterned films are selectively formed at intervals on the main surface of the semiconductor substrate. This pattern film includes at least a pattern film for alignment marks for exposure processing. Using a portion of this patterned film as a mask, a second conductivity type impurity is doped into the semiconductor substrate. The pattern film for alignment marks is left, and the other pattern films are removed. The second conductivity type impurity doped into the semiconductor substrate is distributed to form a second conductivity type semiconductor region. Thereby, the semiconductor substrate is divided into a first conductivity type semiconductor region and a second conductivity type second semiconductor region having a main surface on the same level as the main surface of the first semiconductor region.

[Function] In this invention, the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type are
The main surfaces of the conductive type semiconductor regions are on the same water coating. Therefore, in the boundary region between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, a step portion whose level changes from one semiconductor region to the other semiconductor region is not formed. Therefore, no residue of the deposited layer formed in the subsequent process is generated at the boundary between the semiconductor regions. As a result, the occurrence of electrical short circuits can be prevented.

Further, according to the manufacturing method of the present invention, the pattern film used to form the second conductivity type semiconductor region in the semiconductor substrate is formed to include alignment marks for exposure processing. Therefore, an alignment mark for photolithography can be formed without forming the step 2 at the boundary portion of the semiconductor region.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIGS. A to 1L are cross-sectional views showing, in order of steps, a method of manufacturing a semiconductor memory device according to the present invention, for example, a method of manufacturing a CMOS type DRAM having a memory cell capacitor in a trench. Also, FIGS. 2A to 2A are semiconductors according to the present invention, ? C! A method of manufacturing a storage device, for example,
FIG. 3 is a cross-sectional view showing a method for manufacturing a CMO3 type DRAM having stacked capacitors in the order of steps. Both cross-sectional views show the cross section along the VT-Vl line in FIG. 5B.

First, referring to FIG. 1A, an underlying oxide film 12 is formed on a P-type silicon substrate 1 by a thermal oxidation method or the like. A pattern film, for example, polysilicon l111, is formed on the underlying oxide film 12 by a chemical vapor deposition method or the like.
5 is formed.

Next, referring to FIG. 1B, after a resist film 14 is deposited on polysilicon film 15, polysilicon film 15 and resist film 14 are selectively removed according to a predetermined pattern. Using these patterned films as a mask, N-type impurity ions such as phosphorus ions or arsenic ions are implanted onto the P-type silicon substrate 1 in the direction shown by the arrow at an accelerating voltage of 10 to 200 keV. At this time, ion implantation may be performed after the underlying oxide film 12 is also selectively removed.

Furthermore, referring to FIG. 1C, the resist film 14 is removed.

Thereafter, referring to FIG. 1D, a resist film 14 is deposited on the region where N-type impurity ions are implanted and the region of the dicing line where alignment marks are to be formed. After that, after the polysilicon film 15 is removed, P-type impurity ions such as boron ions are deposited at 10 to 200 K in the direction indicated by the arrow using the resist film 14 as a mask.
It is implanted onto the P-type silicon substrate 1 at an accelerating voltage of about eV.

As shown in FIG. 1E, resist film 14 and underlying oxide film 12 are removed. Then, by subjecting the P-type silicon substrate 1 to heat treatment, the implanted N-type impurity ions and P-type impurity ions are thermally diffused. As a result, a P-type well layer 2 and an N-type well layer 3 are formed in the P-type silicon substrate 1. At this time, alignment marks 21 made of an oxide film and a polysilicon film are formed in the dicing line region.

Referring to FIG. 1F, P-type well layer 2 and N-type well layer 3
A P-type impurity diffusion region 5 is formed as an inversion prevention layer at the boundary between the two regions, and an isolation field oxide film 4 is formed thereon. Although not shown, a field oxide film for isolating between memory cells and a field oxide film for isolating elements such as transistors are also formed at the same time.

Next, as shown in FIG. 1G, a trench is formed in the P-type well layer 2. At the bottom of this trench, a P-type impurity diffusion region 5 is formed as an inversion prevention layer by ion implantation or the like.
is formed. A thick isolation oxide film 4 for element isolation is formed on this P-type impurity diffusion region 5. After forming an N-type impurity diffusion region 6, which will become one electrode of the capacitor, on the side wall of the trench by ion implantation or the like,
A capacitor dielectric film 11 is formed thereon by a thermal oxidation method, a chemical vapor deposition method, or the like. A polysilicon material containing conductive impurities such as phosphorus and arsenic is deposited on the capacitor dielectric film 11 by a method such as chemical vapor deposition, and then selectively removed. Cell plate 9, ie, the other electrode of the capacitor, is formed. In this way, a memory cell capacitor is formed within the trench.

Next, referring to FIG. 1H, on the entire surface of the silicon substrate,
An embedded deposited layer 16 composed of an oxide film, an electrode material such as polysilicon feed, or a composite structure thereof, such as a multilayer structure of a relatively thin oxide film and an electrode material.
a is formed.

Thereafter, as shown in FIG. 1, the buried deposited layer 16a is removed by etching back. As a result, a buried isolation layer 16 filling only the inside of the trench is formed. In this etching process, since no step is formed at the boundary between the P-type well layer 2 and the N-type well layer 3,
No residue of the buried sediment layer is generated at the boundary.

Thereafter, referring to FIG. 1J, an insulating film 17a is formed over the entire surface of the silicon substrate by a method such as thermal oxidation, and then a polysilicon film 15 is deposited thereon. A resist film 14 is formed on the polysilicon film 15 according to a predetermined pattern.

As shown in FIG. 1K, etching is performed using the resist film 14 as a mask, so that the region of the P-type well layer 2 serving as the memory cell formation region is filled with the gate electrode and the word line 20 integrally formed with the electrode. Insulating films 17 are formed at intervals.

Furthermore, a gate insulating film 17 and a gate electrode 7 are formed in the region of the N-type well layer 3. At this time, in the etching process, since no stepped portion is formed in the boundary region between the P-type well layer 2 and the N-type well layer 3, residues of the polysilicon film and the insulating film are generated in the boundary region. Not at all.

Finally, as shown in Figure 51L, an N-channel MOS transistor forming each memory cell is formed in the region of the P-type well layer 2 so as to be connected to the capacitor in the trench formed as described above. Ru. This N channel M
OS) The transistor has a word line 20 as a gate electrode.
and N-type impurity diffusion regions 61 and 62 which become drain or source regions. In one N-type impurity diffusion region 62 constituting the N-channel MOS transistor,
Through the contact hole C, it is connected to a bit line 30 made of an aluminum layer or the like formed on an interlayer insulating film 18 made of a silicon oxide film. - On the other hand, in regions other than the memory cell formation region, for example, in the region of the N-type well layer 3, P-channel MOs constituting peripheral circuits, etc.
A 3I-transistor is formed. This P channel MOS
The transistor is composed of a gate electrode 7 and P-type impurity diffusion regions 51 and 52 serving as source/drain regions in the N-type layer 3.

In this way, a CMO3 type DRAM is formed in which no stepped portion is formed in the boundary region of the well layer and the capacitor of the memory cell is in the trench.

Next, as another example of a semiconductor memory device according to the present invention, a CMO3 type D having a stacked capacitor
A method for manufacturing RAM will be explained.

First, referring to FIG. 2A, underlay oxides 11 and 12 are formed on P-type silicon substrate 1 by a thermal oxidation method or the like.

A nitride film 13 is formed on the underlying oxide film 12 by a chemical vapor deposition method or the like.

Next, referring to FIG. 2B, nitride film 13 and underlying oxide film 12 are selectively removed according to a predetermined pattern using photolithography. At this time, in the memory cell formation region, the nitride film 13 and the like are removed so that the main surface of the P-type silicon substrate 1 in the region to be the element isolation region is exposed.

Moreover, the P-type silicon base in the boundary region of the well layer formed in a later process, that is, the region for separating the well layer! The nitride film 13 is formed so that the main surface of the nitride film 121 is exposed.
etc. are selectively removed. Furthermore, within the dicing area, nitriding J1%=13 according to a predetermined pattern.
Alignment marks 21 are formed by selectively removing the marks and the like.

Furthermore, referring to FIG. 2C, a resist film 14 is formed so that only the region where the N-type well layer is to be formed is exposed. Thereafter, using a high-energy ion implantation device, N-type impurity ions such as phosphorus ions or arsenic ions are implanted in the direction indicated by the arrow using the resist film 14 as a mask.
．． It is implanted onto the P-type silicon substrate 1 at an accelerating voltage of 3 to IMeV. At this time, the film thicknesses of the nitride film 13 and the underlying oxide film 12 are each 500 to 1500 Å so that ions having the above energy pass through.

The number is set at 200-500 people. In addition, the thickness of the resist film 14 is set to 3 to 5 mm so that the implanted ions do not pass through.
It is set to μm.

Referring to FIG. 2D, the resist film 14 used as a mask for implanting N-type impurity ions is removed. Then, conversely, the resist film 14 is formed so that the main surface of the P-type silicon substrate 1 in the region where the P-type well layer is to be formed is exposed.
is deposited. Using this resist JJ414 as a mask, 0.2 to 0.5 P-type impurity ions such as boron ions
It is implanted onto the P-type silicon substrate 1 at an accelerating voltage of approximately MeV. At this time, the thickness of the resist film 14 used as a mask is approximately the same as the thickness of the resist film 14 shown in FIG. 2C.

As shown in FIG. 2E, after the resist film 14 is removed, the P-type silicon substrate 1 is subjected to heat treatment, so that the implanted N-type impurity ions and P-type impurity ions are thermally diffused. As a result, a P-type well layer 2 and an N-type well layer 3 are formed in the P-type silicon substrate 1. At this time, an isolation field oxide film 4 is formed at the boundary between the P-type well layer 2 and the N-type well layer 3 and in the element isolation region.
1.42 is formed. At the same time, an alignment mark pattern made of a thick oxide film 43 is formed in the alignment mark forming region p11.

Thereafter, as shown in FIG. 2F, a resist film 14 is formed so that only the region where the anti-inversion layer is to be formed under the isolation field oxide films 41 and 42 is exposed. Using this resist film 14 as a mask, P-type impurity ions such as boron ions are implanted using a high-energy ion implantation device so as to pass through the isolation field oxide films 41 and 42. At this time, the acceleration voltage for ion implantation is 0.1 to 0.
It is about 5M eV. The thickness of the resist film 14 used as a mask is set to a thickness that does not allow ions having the above energy to pass through, and is about 2 to 5 μm. Furthermore, field oxidation for isolation is 11%41.
The film thickness of 42 is set to be sufficient to allow ions having the above-mentioned energy to pass through, and is approximately 0°2 to 1.0 μm.

In this way, as shown in FIG. 2G, after the P-type well layer 2 and the N-type well layer 3 are formed and the isolation field oxide films 41 and 42 are formed, the isolation field oxide film 41 and 42 are formed. , 42, a P-type impurity diffusion region 5 for preventing inversion is formed.

Thereafter, as shown in FIG. 2H, nitride Pl! 13. The underlying oxide film 12 is removed.

Referring to FIG. 21, an insulating film 1 is formed on the entire surface of the silicon substrate.
After 7a is formed by a method such as thermal oxidation, a polysilicon film 15 is deposited. Furthermore, polysilicon film 1
An insulating film 17b is deposited on top of the insulating film 17b. A resist film 14 according to a predetermined pattern is formed on the insulating film 17b.

Then, as shown in FIG. 2J, etching is performed using the resist film 14 as a mask, so that a word sandwiched between the gate insulating films 17 is formed in the region of the P-type well layer 2 serving as a memory cell formation region. Lines 20 are formed at intervals. Further, in the region of the N-type well layer 3, a gate electrode 7 and a gate insulator H17 are similarly formed.

Finally, secondly, referring to the figure, in the region of the P-type well layer 2, an N-channel MO3I-transistor and a stacked capacitor constituting each memory cell are formed. This N
The channel MOS transistor is composed of a word line 20 as a gate electrode and N-type impurity diffusion regions 61 and 62 as drain or source regions. Further, the stacked capacitor connected to the N-channel MOS transistor is connected to the N-type impurity diffusion region 61, and extends over the storage node 8, which is one electrode formed from a conductive layer such as polycrystalline silicon. A cell plate 9 serving as the other electrode formed from a similar conductive layer;
It is composed of a storage node 8 and a capacitor dielectric film 11 made of a nitride film or the like sandwiched between cell plates 9.

One N-type impurity diffusion region 62 constituting the N-channel MO3t-transistor is connected via a contact hole C to a bit line 30 made of an aluminum layer or the like formed on an interlayer insulating film 18 made of a silicon oxide film. be done. On the other hand, in a region other than the memory cell formation region, a P-channel MOS transistor constituting a peripheral circuit etc. is formed in the region of N-type well layer 3. This P-channel MOS transistor is composed of a gate electrode 7 and P-type impurity diffusion regions 51 and 52 serving as source/drain regions in the N-type well layer 3.

In this way, a CM with a stacked capacitor in which no stepped portion is formed at the boundary portion of the well layer.
OS'42 DRAM is formed.

In addition, in the above two examples of CMOS type DRAM, an example is shown in which a P-type well layer and an N-type well layer are formed in a P-type silicon substrate, but an N-type well layer and an N-type well layer are formed in a P-type silicon substrate.
A CMOS type DRAM in which only a type well layer is formed may also be used. In addition, in the above embodiment, an example using a P-type silicon substrate was shown, but a CM using a reverse N-type silicon substrate was shown.
O3 Type O3 Type DRA The semiconductor memory device and its manufacturing method according to the present invention described above are summarized as follows.

(1) A semiconductor substrate of a first conductivity type having a main surface; a semiconductor region of a second conductivity type formed on the semiconductor substrate; A semiconductor memory device, wherein the semiconductor substrate is divided into a second semiconductor region of a second conductivity type having a main surface on the same level as a main surface of the first semiconductor region.

(2) The semiconductor memory device according to (1), further comprising an isolation insulating film formed on the main surface of the semiconductor substrate in a boundary region between the first semiconductor region and the second semiconductor region.

(3) The semiconductor memory device according to (1), wherein the memory element includes a field effect semiconductor element formed within the first semiconductor region.

(4) The field effect semiconductor element includes an impurity region of a second conductivity type formed in the first semiconductor region (
3) semiconductor memory device.

(5) The field effect semiconductor element includes an insulated gate, one electrode and the other electrode formed on the main surface of the semiconductor substrate at a distance below the insulated gate, The impurity region of the second conductivity type constitutes the one electrode and the other electrode, and a channel region is formed in the first semiconductor region between the one electrode and the other electrode. ) Semiconductor storage device (6) The storage element is ? The semiconductor memory device according to (5), including a capacitor connected to one electrode of jJ.

(7) The semiconductor memory device according to (6), wherein the capacitor includes a capacitor formed along a sidewall of a trench formed in the first semiconductor region.

(8) The capacitor includes a second conductivity type impurity region formed on the side wall of the trench, a dielectric film formed on the second conductivity type impurity region, and a dielectric film formed on the second conductivity type impurity region. The semiconductor memory device according to (7), further comprising a capacitor having a trench structure formed of a conductive film formed therein, and in which the impurity region of the second conductivity type is connected to the one electrode.

(9) The capacitor has a laminated structure formed of one conductive film and the other conductive film sandwiching a dielectric film, and the one conductive film is connected to the negative electrode. The semiconductor memory device of (6), including the capacitor.

(10) providing a semiconductor substrate of a first conductivity type having a main surface; selectively spaced apart on the main surface of the semiconductor substrate;
The pattern film includes at least a pattern film for an alignment mark for exposure processing, and a part of the pattern film is used as a mask to form an impurity of a second conductivity type. doping into the semiconductor substrate, leaving the pattern film for the alignment mark and removing the other pattern film, distributing the doped second conductivity type impurity into the semiconductor substrate, By forming a semiconductor region of a second conductivity type, a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type having a main surface on the same level as the main surface of the first semiconductor region are formed. and dividing the semiconductor substrate.

(11) The step of forming the pattern film includes forming a first pattern film for forming an isolation insulating film, and forming a second pattern film for alignment marks for exposure and light processing. The method of manufacturing a semiconductor memory device according to (10), including the steps of:

(12) The step of doping the second conductivity type impurity into the semiconductor substrate includes the step of implanting second conductivity type impurity ions having enough energy to pass through the first pattern film. 11) The method for manufacturing a semiconductor memory device.

(13) The method for manufacturing a semiconductor memory device according to (11), further comprising the step of forming the isolation insulating film using the first pattern film as a mask.

(14) The method for manufacturing a semiconductor memory device according to (13), further comprising the step of forming a first conductivity type high concentration impurity region under the isolation insulating film.

(15) The step of forming the high concentration impurity region of the first conductivity type includes the step of implanting impurity ions of the first conductivity type having enough energy to pass through the isolation insulating film. A method for manufacturing a semiconductor memory device.

(16) The method for manufacturing a semiconductor memory device according to (10), further comprising the step of forming a highly doped semiconductor region of a first conductivity type in the semiconductor substrate.

(17) In the step of forming the first conductivity type high concentration semiconductor region, the first conductivity type impurity is added to the first conductivity type impurity by using the patterned film formed on the main surface of the second semiconductor region as a mask. (1) including the step of doping into the semiconductor substrate.
6) The method for manufacturing a semiconductor memory device.

(18) The method for manufacturing a semiconductor memory device according to (10), further comprising a step of forming the memory element.

(19) The method of manufacturing a semiconductor memory device according to (18), wherein the step of forming the memory element includes a step of forming a field effect semiconductor element and a capacitor connected thereto in the first semiconductor region.

(20) The step of forming the beef yabashita includes the step of forming the first
A method of manufacturing a semiconductor memory device, including the step of forming a trench in a semiconductor region.

[Effects of the Invention] As described above, according to the present invention, the main surfaces of the semiconductor regions of two different conductivity types are on the same level, so that a step portion is not formed in the boundary region between the semiconductor regions. There isn't. Therefore, no deposit residues will be formed in the step portion, which will be formed in subsequent steps. therefore,
It does not cause electrical short circuits or deterioration in the performance of semiconductor devices. Further, according to the present invention, alignment marks for mask alignment for photolithography can be easily formed without forming step portions between semiconductor regions.

[Brief explanation of the drawing]

Figure 1A, Figure 1B, Figure 1C, Figure 1D, Figure 1E,
Figure 1F, Figure 1G, Figure 1H, Figure 1I, Figure 1J,
1K and 1L show a method of manufacturing a semiconductor memory device according to the present invention, for example, a CMO8 type O8 type DRA having a trench capacitor cell. Figure 2E,
Figure 2F, Figure 2G, Figure 2H, Figure 2I, Figure 2J,
The second figure shows another embodiment of the method for manufacturing a semiconductor memory device according to the present invention, for example, a CMO8 type O8 type DRA having stacked capacitor cells. FIG. 3 is a block diagram showing the overall configuration of a conventional DRAM. FIG. 4 is an equivalent circuit diagram corresponding to one memory cell of the DRAM shown in FIG. 3. FIG. 5A is a plan view showing a wafer on which a plurality of DRAM chips are formed. FIG. 5B is a partial plan view showing the portion VB in FIG. 5A. Figure 6A, Figure 6B, Figure 6C, Figure 6D, Figure 6E,
Figure 6F, Figure 6G, Figure 6H, Figure 61, Figure 61,
Figures 6 and 6L show a conventional method of manufacturing a semiconductor memory device, for example, a CM for manufacturing a trench capacitor cell.
O5 type O5 type DRA Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D, Fig. 7E, Fig. 7F, Fig. 7G, Fig. 7H, and Fig. 7 show the conventional manufacturing method of a semiconductor memory device. Another example of, e.g., C to H a stacked capacitor cell
It is a sectional view showing MO5 type O5 type DRA. In the figure, 1 is a P-type silicon substrate, 2 is a P-type well layer, 3 is an Nm well layer, ]3 is a nitride film, 14 is a 1/cyst film, and 15 is a polysilicon film. In each figure, the same reference numerals indicate the same or corresponding parts. Figure 1A Figure 1C Figure 1D Figure 15 CP type hollow point fi 3:N↑zlL layer 1st G
figure)
j Figure 6A Figure 60 Figure 6E Figure 6F t j Figure 6G Figure 6H Figure 61 Figure 6j Figure 6

Claims (2)

[Claims] (1) A semiconductor substrate of a first conductivity type having a main surface, and a semiconductor region of a second conductivity type formed in the semiconductor substrate, the first semiconductor region of the first conductivity type and the first semiconductor region. The semiconductor substrate is divided into a second semiconductor region of a second conductivity type having a main surface on the same level as the main surface of the semiconductor memory device. (2) preparing a semiconductor substrate of a first conductivity type having a main surface; selectively spaced apart on the main surface of the semiconductor substrate;
forming a patterned film, the patterned film including at least a patterned film for an alignment mark for exposure processing, and using a part of the patterned film as a mask to form an impurity of a second conductivity type. doping into the semiconductor substrate, leaving the pattern film for the alignment mark and removing the other pattern film, distributing the doped impurity of the second conductivity type into the semiconductor substrate, By forming a semiconductor region of a second conductivity type, a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type having a main surface on the same level as the main surface of the first semiconductor region are formed. and dividing the semiconductor substrate.