JPS63205966A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an isolation region from being spread in the transverse direction by a method wherein a p-type well region to form a MOSFET and the isolation region are formed after impurities of almost equal concentration have been diffused. CONSTITUTION:After ions of boron have been implanted into a region to form a p-type well on the surface of an n-type silicon substrate 1 and ions of phosphorus have been implanted into a region other than the region to form the p-type well, p-type well regions 6, 7 and isolation regions 3 are formed. In order to make the surface concentration of the impurities and the diffusion depth equal at the regions 6, 7, 3, the implantation volume of ions and the diffusion condition are controlled. Then, an n-channel MNOS nonvolatile storage device is formed on the surface of the region 6; an n-channel MOSFET is formed on the surface of the region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an MIOS (metal-insulator-silicon oxide film-semiconductor) type volatile memory element and an MIS (metal-insulator-semiconductor) type field effect transistor. The present invention will be applied to the manufacturing method of semiconductor integrated circuits that aim at high integration.

Conventional technology With the rapid progress of LSI technology, the performance and functionality of semiconductor integrated circuits are increasing, and MIO3 on the same chip is becoming more sophisticated.
IO3 All non-volatile storage elements with electrically rewritable RO
M (EEFROM) and M such as microcomputers
There is an increasing demand for semiconductor integrated circuits that have a control circuit function using IS type field effect transistors. Note that as a MIOS type nonvolatile memory element, a thin silicon oxide film that can be used as a tunneling medium is formed on a silicon substrate, a silicon nitride film is formed on it, and a gate electrode is further formed on it.
Nonvolatile memory transistors having a silicon nitride film-silicon oxide film-semiconductor structure are often used.

Further, as a MIS type field effect transistor, an MO3 type field effect transistor in which a silicon oxide film is formed on a silicon substrate and a gate electrode is formed thereon is often used. In order to realize a semiconductor integrated circuit in which a memory circuit section consisting of all MNO8NO8 non-volatile memory elements and a peripheral circuit section consisting of MO3 type field effect transferers coexist on the same substrate, it is necessary to It is necessary to electrically separate them from the type field effect transistor. Conventionally, as shown in FIG. 3, a P-type epitaxial layer 2 is grown on an n-type silicon substrate 1, and n-type impurities are selectively added into the epitaxial layer 2 so as to penetrate the epitaxial layer 2. An MNO8 type nonvolatile memory element 4 is formed in the first island region of the epitaxial layer surrounded by the isolation region 3, and an isolation region 3 is formed by diffusion into the epitaxial layer surrounded by the isolation region 3. A manufacturing method is well known in which the MO8 field effect transistor 5 is formed in the second island region to separate each element.

Problems to be Solved by the Invention In the conventional manufacturing method, the thickness of the epitaxial layer 2 is required to be 10 to 15 μm, so the isolation region 3 that separates the elements becomes a very deep diffusion layer, and accordingly, the isolation region 3 is formed. The lateral diffusion caused by the separation region 3 also becomes very large, which increases the area required to form the isolation region 3, resulting in a drawback that the degree of integration is not very high.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit, which aims to reduce the area of the isolation region necessary for an MTO8 type nonvolatile nonvolatile memory element and achieve higher integration.

Means for Solving the Problems The method for manufacturing a semiconductor integrated circuit of the present invention includes forming first and second well regions of a conductivity type opposite to that of the semiconductor substrate from the surface to the inside of a semiconductor substrate of one conductivity type; An isolation region is formed by diffusing an impurity of one conductivity type in a region other than the first and second well regions at an impurity concentration substantially equal to that of the impurity of the opposite conductivity type, and an MI in the first well region is formed.
An OS type nonvolatile memory element is formed, and a MIS type field effect transistor of one conductivity type is formed in the second well region.

According to the method for manufacturing a semiconductor integrated circuit of the present invention, MIO3
The lateral diffusion in the well region of the non-volatile memory element and MIS field effect transistor formation region and the lateral diffusion in the isolation region cancel each other out because their impurity concentrations are almost equal, and the lateral diffusion is almost completely suppressed. This allows the area of the isolation region required for isolation to be reduced.

Embodiment An embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to the sectional view of FIG. First, n-type silicon substrate 1
Boron ions are implanted into the P-type well formation region on the surface of the P-type well, and phosphorus ions are implanted into the regions other than the P-type well formation region, and then drive-in is simultaneously performed to form the first and second P-type well regions 6. 7 and an isolation region 3 of the n-type well region are formed. Note that the surface concentration of impurities in both the first and second P-type well regions 6 and 7 and the isolation region 3 is approximately I x 10"c+a-
3, the ion implantation amount and diffusion conditions are controlled so that the diffusion depth is approximately 10 μl.

By making the impurity concentrations equal in this way, the lateral diffusion of the P-type well region and isolation region is offset.

This makes it possible to suppress lateral spread due to diffusion.

Next, an n-channel MNO5 type nonvolatile memory element is placed in the surface area of the first P-type well region 6, and an n-channel MO8 type field effect element is placed in the surface area of the second P-type well region 7. Form a transistor. This MNO3 type nonvolatile memory element is formed by the following method. First, a silicon oxide film 8, which will become a gate insulating film, is formed on the surface of the P-type well region 6 to a thickness of about 20 Å so that it can serve as a tunneling medium for the MNO8 type nonvolatile memory element. Further, a silicon nitride film 9 on the silicon oxide film 8 is formed to a thickness of about 500 Å by a vapor phase growth method based on a chemical reaction between silane (SiH4) and ammonia (NH3). After forming a polysilicon film on silicon nitride film 9, phosphorus ions are selectively implanted to form source region 11, drain region 12, and gate electrode 10. Due to the above, M
A NO3 type nonvolatile memory element is formed.

The n-channel MO3 type field effect transistor formed on the surface region of the second P-type well region 7 has a silicon oxide film 81, which becomes a gate insulating film, formed on the surface of the P-type well region 7. After forming a polysilicon film thereon, phosphorus ions are implanted to form the source region 11 and drain region 12.
and gate electrode 10. Note that in manufacturing the MNOs type nonvolatile memory element and the MO3 type field effect transistor, the gate electrode 10,
Source region 11 and drain region 12 are formed simultaneously. Furthermore, since the silicon oxide films 8 and 81 have different thicknesses, they are formed in two parts.

Although the above-mentioned embodiment I is a case where the MO3 field effect transistor is an n-channel type, it can also be realized by a CMO3 (complementary MO8) type as shown in FIG. 2 as another embodiment. That is, by adding a P-channel MO8 field effect transistor to the surface region of the n-type well region that is the isolation region 3, a CMOS type semiconductor integrated circuit can be formed. M of this P channel
The O3 type field effect transistor has a silicon oxide film 82 serving as a gate insulating film on the surface of the isolation region 3 of the n-type well region.
A polysilicon film doped with phosphorus is formed on this film to form the gate electrode 10, and then boron ions are selectively implanted into the isolation region 3 to form the source region 13 and drain region 14. is formed by forming. Next, a CMO3 circuit can be constructed by complementarily connecting the n-channel MO8 type field effect transistor and the P-channel MO8 type field effect transistor with metal wiring.

In addition, in the example, as an MIO3 type nonvolatile memory element,
Although we have described the case where an MNO8 type nonvolatile memory element is used, a high dielectric constant film such as aluminum oxide (Ae203) or tantalum oxide (Ta20s) may be used instead of the silicon nitride film as the gate insulating film. Needless to say.

Effects of the Invention According to the method for manufacturing a semiconductor integrated circuit of the present invention, MIO3
In order to form the P-type well region forming the MO8-type field effect transistor constituting the non-volatile memory element and the peripheral circuit, and the isolation region separating them, by diffusing impurities at approximately the same concentration, the isolation region is Since the construction method is suppressed, the area required for separating the MIOS type nonvolatile memory elements can be significantly reduced, and high integration becomes possible.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 3 is a cross-sectional view showing a conventional method for manufacturing a semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 3... Separation region, 6... First P-type well region, 7...
...Second P-shaped well region, 8,81.82...
...Silicon oxide film, 9...Silicon nitride film,
10...Gate electrode, 11.13...
Source region, 12.14...Drain region. Name of agent: Patent attorney Toshio Nakao 1 person/-n*
Silicon Grave Scrap--P Shape Taxi 2νI J--to Ivy-1 Negative 1 Hetranzizuku

Claims (3)

[Claims] (1) Diffusing impurities of a conductivity type opposite to that of the semiconductor substrate from the surface of a semiconductor substrate of one conductivity type to form first and second well regions, and to form regions other than the first and second well formation regions. an isolation region is formed by diffusing an impurity of one conductivity type into the region at an impurity concentration substantially equal to that of the impurity of the opposite conductivity type; a MIOS type nonvolatile memory element is formed in the first well region; 1. A method of manufacturing a semiconductor integrated circuit, characterized in that a MIS field effect transistor of one conductivity type is formed in a well region of a semiconductor integrated circuit. (2) A method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that a MIS field effect transistor of a conductivity type opposite to that of the semiconductor substrate is formed in the isolation region. (3) MIOS type nonvolatile memory element is MNOS (metal-
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the nonvolatile memory element is a silicon nitride film-silicon oxide film-semiconductor type.