JPS6116520A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the superposition of semiconductor device with high precision while making resist coating shapes at both sides of a basic pattern symmetrical by a method wherein once coated resist is forced to resume flowing. CONSTITUTION:Phenol novolak base positive type photo resist 4 is dripped on a wafer 1 to be turned at around 5,000rpm for 3sec for coating the wafer 1. After a spinner stops turning, the resist 4 resumes flowing to be formed into symmetrical shapes at both sides of pattern. In such a status, the resist 4 is continuously prebaked to thoroughly remove any residual solvent. The interval between the coating and prebaking processes may be within 20sec. Through these procedures, the resist film thickness at both sides of basic alignment pattern 2 may be equalized to make the actual mark center C0 and the apparent pattern center C' correspond with each other providing superposition of semiconductors with high precision. The coating time may be recommended for 2-5sec. Besides, any resist film exceeding 2mum thick will not be practical in terms of the signal intensity level of chip alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a photoresist coating process in photolithography using a reduction projection exposure apparatus, in which the shape of resist coating on both sides of a base pattern is made symmetrical. The present invention relates to a method capable of improving mask overlay accuracy.

Conventional Structure and Problems Photoresist coating in the semiconductor device manufacturing process has conventionally been carried out by using a spinner and spinning for 20 to 40 seconds to sufficiently remove the solvent.

In this method, on the base pattern along the rotational direction of the wafer, the shape of the resist coating on both sides of the pattern is different, and the resist film thickness is different. For this reason, in the subsequent chip-by-chip alignment process using a through-the-lens method using a reduction projection exposure apparatus, an overlay error occurs due to the asymmetry of the resist film thickness on both sides of the underlying alignment pattern.
There is a problem in that it cannot cope with the increase in the degree of integration and miniaturization of integrated circuits.

FIG. 1 is a cross-sectional view showing the state of resist coating on both sides of the base alignment pattern when the conventional method is used, and the resist film thickness is about 1 μm. As shown in the figure, because the resist film thickness is different on both sides of the pattern, when performing chip-by-chip alignment (monochromatic light is used as alignment light) using a reduction projection exposure system, the apparent center of the pattern (Fig. △ between C) and the actual pattern center (Go in the figure)
A deviation of L occurs. This amount of deviation ΔL varies within the wafer (particularly at the distance from the center of the wafer), which causes a decrease in the actual overlay accuracy.

Purpose of the Invention The present invention aims to solve the above-mentioned problems, and provides a semiconductor that achieves highly accurate overlay by making the resist coating shape on both sides of the base pattern the same and eliminating the difference in resist film thickness. A method for manufacturing the device is provided.

Structure of the Invention In short, the present invention is capable of applying a resist by rotating a spinner for several seconds, completely removing the solvent in the resist, and causing reflow of the resist after application.
The resist coating shape on both sides of the base pattern is the same (symmetrical)
A method of manufacturing a semiconductor device is characterized in that:

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained with reference to examples.The present invention is explained by first using a conventional phenolic novolac thread positive type photoresist on a wafer with a thickness of about 1 .mu.m, as in the conventional method. FIG. 2 shows the state immediately after spin coating. Although FIG. 2 is the same in shape as FIG. 1, the solvent in the resist has not been completely removed, and the resist film is in a fluid state. Therefore, after the spinner stops rotating, the resist reflows, and the resist is in the most stable state, that is, in a symmetrical shape on both sides of the pattern. (Figure 3) In this state,
The subsequent prebake treatment is performed continuously to completely remove the remaining solvent in the resist. In this example, the interval between resist application and pre-bake treatment was 5 seconds, but it has been experimentally confirmed that there is no problem if the interval is within 20 seconds.

According to the present invention, the resist film thickness on both sides of the underlying alignment pattern is the same (symmetrical), and
As shown in the figure, the actual mark center and the apparent (optical image) pattern center match, allowing highly accurate overlay.

In this example, the coating time was 3 seconds, but if it is less than 2 seconds, there will be large variations in the resist film thickness, and if it exceeds 5 seconds, there will be asymmetry in the resist film thickness on both sides of the pattern. , preferably 2 seconds or more and 5 seconds or less. Further, unless the resist film thickness is 2 μm or less, it is too large for practical purposes in terms of signal strength for chip alignment.

In addition to the effects of the invention, the present invention can improve the precision of chip-by-chip alignment using the through-the-lens method of reduction projection exposure equipment, which will become the mainstream in the future for ultra-I and SI bonding processes with fine element structures. It is particularly effective and has high industrial value.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the state of resist coverage on both sides of the underlying alignment pattern when performed using the conventional method, Figures 2 and 3.
The figure is a cross-sectional view of the process of the present invention, and FIG. 4 is a cross-sectional view showing the state of resist coating on both sides of the base alignment pattern according to the present invention. 1... Semiconductor substrate, 2... Alignment pattern provided on wafer, 3...
Resist after the solvent has been removed, 4...Resist where the solvent has not been completely removed. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure C Figure 2 Figure 4 C,=C' ゛ 1

Claims (5)

[Claims] (1) After photoresist coating in the photolithography process using a reduction projection exposure device is performed by spinner rotation (short spin), heat treatment (soft bake) is continuously performed to uniformize the thickness of the photoresist at both ends of the pattern on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, characterized in that: (2) The method for manufacturing a semiconductor device according to claim 1, wherein the spinner rotation time is 2 seconds or more and 5 seconds or less. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the time interval between resist application and heat treatment is 20 seconds or less. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the photoresist is a positive resist using a phenol novolak resin as a base resin and a quinone diazide resin as a dissolution inhibitor. . (5) The method for manufacturing a semiconductor device according to claim 1, wherein the photoresist coating thickness is 2 μm or less.