JPS61263223A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61263223A JPS61263223A JP60104048A JP10404885A JPS61263223A JP S61263223 A JPS61263223 A JP S61263223A JP 60104048 A JP60104048 A JP 60104048A JP 10404885 A JP10404885 A JP 10404885A JP S61263223 A JPS61263223 A JP S61263223A
- Authority
- JP
- Japan
- Prior art keywords
- film
- positive resist
- pattern
- polyimide film
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229920001721 polyimide Polymers 0.000 claims abstract description 27
- 239000004642 Polyimide Substances 0.000 claims abstract description 5
- 230000035945 sensitivity Effects 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000003431 cross linking reagent Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- -1 4' azidobiphenyl sulfide Chemical compound 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ポリイミド膜の高精度パターニングを、ポリイミド膜上
に架橋剤を含有するポジレジスト膜を近紫外光と遠紫外
光を照射し、現像することによって行なう。[Detailed Description of the Invention] [Summary] High-precision patterning of a polyimide film is performed by irradiating a positive resist film containing a crosslinking agent on the polyimide film with near-ultraviolet light and far-ultraviolet light, and developing the film.
本発明は半導体装置の製造方法に係り、特に半導体基板
上に形成されるポリイミド層を高精度にパターニングす
る方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of patterning a polyimide layer formed on a semiconductor substrate with high precision.
ポリイミド系樹脂は耐熱性・耐薬品性・強度・電気絶縁
性等に優れ、純度を高める努力も為されたため、近年半
導体デバイスの材料としても用いられるようになってき
た。ＬＳＩ用として前工程で用いられる場合、単に被膜
を塗布するだけでなくパターンを形成しなければならな
い。パターンを形成する例えばウェットエツチング法で
はそのエッチャントとしてポジレジスト用現像液とヒド
ラジン系のものが多用されている。Polyimide resins have excellent heat resistance, chemical resistance, strength, electrical insulation, etc., and efforts have been made to improve their purity, so in recent years they have come to be used as materials for semiconductor devices. When used in a pre-process for LSI, it is necessary not only to simply apply a film but also to form a pattern. For example, in the wet etching method for forming a pattern, a positive resist developer and a hydrazine-based etchant are frequently used.
ポジレジスト用現像液を用いるポリイミド膜のパターン
形成工程では、工程短縮のためにポジレジストをマスク
として使用し、該ポジレジストの現像工程に続けてポリ
イミド膜のエツチングを行なう。しかしながらポリイミ
ド膜の下地の材質が例えばアルミニウム配線層、リン珪
酸ガラス（ＰＳＧ）層、シリコン基板等種々の場合があ
るため、該下地材質に対する光の反射の影響を受けてポ
ジレジストに対して均一の露光効果が得られない。In the polyimide film pattern formation process using a positive resist developer, the positive resist is used as a mask to shorten the process, and the polyimide film is etched following the positive resist development process. However, since the underlying material of the polyimide film may be various, such as an aluminum wiring layer, a phosphosilicate glass (PSG) layer, or a silicon substrate, it may be affected by the reflection of light on the underlying material, making it difficult to achieve uniformity with respect to the positive resist. The exposure effect cannot be obtained.
その結実現像時ポリイミドのエツチング進行に分布が生
じ所定のパターンから約３０％程度のバラツキを有する
パターンが得られる。When the image is formed and realized, a distribution occurs in the progress of etching the polyimide, and a pattern having a variation of about 30% from a predetermined pattern is obtained.
本発明の目的はポリイミド膜の下地材質に対する光の反
射の影響を受けずに高精度のポジレジストパターン及び
ポリイミド膜パターンを形成する方法を提供することで
ある。An object of the present invention is to provide a method for forming a highly accurate positive resist pattern and polyimide film pattern without being affected by light reflection on the underlying material of the polyimide film.
上記問題点は本発明によればポリイミド以外の複数の材
質領域上に形成されたポリイミド膜をパターニングする
工程を含む半導体装置の製造方法において、該ポリイミ
ド膜上に、遠紫外領域に感度を有する光架橋だ１を含有
するポジレジスト層を形成し、該ポジレジスト層表面を
遠紫外光と近紫外光によって露光し、次に現像すること
によって露光部ポジレジスト層並びに該露光部ポジレジ
スト層下のポリイミド膜をパターニングすることを特徴
とする半導体装置の製造方法によって解決される。According to the present invention, in a method for manufacturing a semiconductor device including a step of patterning a polyimide film formed on a plurality of material regions other than polyimide, the above-mentioned problem is solved by applying light sensitive to the deep ultraviolet region onto the polyimide film. A positive resist layer containing the crosslinked layer 1 is formed, the surface of the positive resist layer is exposed to deep ultraviolet light and near ultraviolet light, and then developed to form the positive resist layer in the exposed area and the area under the positive resist layer in the exposed area. The problem is solved by a method for manufacturing a semiconductor device characterized by patterning a polyimide film.
本発明によれば遠紫外領域に感度を有する光架橋剤を含
有するポジレジスト膜を用い、ポジレジスト膜に近紫外
光と遠紫外光の２種類の光を多量に照射するのでインヒ
ビターの破壊と架橋の両方の反応が起り、ポリイミド膜
の下地材質の影響を受けず前述の両方の光の量的な大小
関係のみによって現像液に対する一定した溶解速度が定
まる。According to the present invention, a positive resist film containing a photocrosslinking agent sensitive to the far ultraviolet region is used, and the positive resist film is irradiated with large amounts of two types of light, near ultraviolet light and far ultraviolet light, so that the inhibitor can be destroyed. Both crosslinking reactions occur, and a constant rate of dissolution in the developer is determined only by the quantitative magnitude relationship of the two types of light described above, without being affected by the underlying material of the polyimide film.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１Ａ図から第１Ｃ図は本発明の一実施例を説明するた
めの工程断面図である。1A to 1C are process sectional views for explaining one embodiment of the present invention.
第１Ａ図に示すようにシリコン基板１上に約１μの厚さ
のＡｌ配線層２が形成されており、更にシリコン基板１
及びＡｌ配線層２、全表面に約２ないし２．５μの厚さ
のポリイミド膜３をスピンコード塗布する。As shown in FIG. 1A, an Al wiring layer 2 with a thickness of about 1 μm is formed on a silicon substrate 1, and
Then, a polyimide film 3 having a thickness of about 2 to 2.5 μm is coated on the entire surface of the Al wiring layer 2 using a spin code.
次に第１Ｂ図に示すように、ポリイミド膜３上に約１μ
の厚さのポジレジスト膜４をスピンコード塗布する。こ
のポジレジストには遠紫外領域に感度を有する光架橋剤
、４′アジドビフエニルスルフイドが約５重量％含有せ
しめられている。次にポジレジスト膜４を約１００℃の
温度２分間、プリベークする。その後ポジレジスト膜４
の除去部（２ケ所）に近紫外光５を約１５秒間一括露光
しパターン転写し、次に遠紫外光６を約０．５秒間全面
照射する。Next, as shown in FIG. 1B, about 1μ
A positive resist film 4 having a thickness of 2 is applied using a spin code. This positive resist contains about 5% by weight of 4' azidobiphenyl sulfide, a photocrosslinking agent sensitive in the deep ultraviolet region. Next, the positive resist film 4 is prebaked at a temperature of about 100° C. for 2 minutes. After that, positive resist film 4
The areas to be removed (two locations) are exposed at once to near ultraviolet light 5 for about 15 seconds to transfer the pattern, and then the entire surface is irradiated with far ultraviolet light 6 for about 0.5 seconds.
次に第１Ｃ図に示すように周知の現像液を用いて現像し
ポジレジスト膜４及びポリイミド膜３をパターニングす
る。その後残存ポジレジスト膜４を除去すれば所定のパ
ターン転写部の精度のよいポリイミド膜のパターンが形
成される。Next, as shown in FIG. 1C, the positive resist film 4 and the polyimide film 3 are patterned by development using a well-known developer. Thereafter, by removing the remaining positive resist film 4, a highly accurate polyimide film pattern is formed at the predetermined pattern transfer portion.
本発明に係る遠紫外露光は遠紫外用アライナ−又は遠紫
外キュア装置を使用し照射時間も短くてよいので工数増
加は小さい。The far-ultraviolet exposure according to the present invention uses a far-ultraviolet aligner or a far-ultraviolet curing device, and the irradiation time may be short, so the increase in man-hours is small.
本発明の実施例ではポジレジスト膜の露光を近紫外光、
そして遠紫外の順に行なったがその順序を逆にしてもよ
く又条件により同時に行なってもよい。In the embodiments of the present invention, the positive resist film is exposed to near ultraviolet light.
Although the steps were carried out in the order of deep ultraviolet, the order may be reversed or they may be carried out simultaneously depending on the conditions.
以上説明したように、本発明によればポリイミド膜の下
地材質の光反射に対する影響を受けずに、高精度パター
ンのポリイミド膜を得ることができる。As described above, according to the present invention, a polyimide film with a highly accurate pattern can be obtained without being affected by the light reflection of the underlying material of the polyimide film.
第１Ａ図から第１Ｃ図は本発明の一実施例を説明するた
めの工程断面図である。
１・・・シリコン基板、 ２・・・Ａｌ配線層、３・
・・ポリイミド膜、 ４・・・ポジレジスト膜、５・
・・近紫外光、 ６・・・遠紫外光。1A to 1C are process sectional views for explaining one embodiment of the present invention. 1... Silicon substrate, 2... Al wiring layer, 3...
...Polyimide film, 4...Positive resist film, 5.
... Near ultraviolet light, 6... Far ultraviolet light.
Claims (1)
リイミド膜をパターニングする工程を含む半導体装置の
製造方法において、 該ポリイミド膜上に、遠紫外領域に感度を有する光架橋
剤を含有するポジレジスト層を形成し、該ポジレジスト
層表面を遠紫外光と近紫外光によって露光し、次に現像
することによって露光部ポジレジスト層並びに該露光部
ポジレジスト層下のポリイミド膜をパターニングするこ
とを特徴とする半導体装置の製造方法。[Scope of Claims] 1. A method for manufacturing a semiconductor device including a step of patterning a polyimide film formed on a plurality of material regions other than polyimide, wherein a photocrosslinking layer having sensitivity in the deep ultraviolet region is formed on the polyimide film. By forming a positive resist layer containing the agent, exposing the surface of the positive resist layer to deep ultraviolet light and near ultraviolet light, and then developing it, the exposed area positive resist layer and the polyimide film under the exposed area positive resist layer are formed. 1. A method for manufacturing a semiconductor device, the method comprising patterning a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60104048A JPS61263223A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60104048A JPS61263223A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61263223A true JPS61263223A (en) | 1986-11-21 |
Family
ID=14370329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60104048A Pending JPS61263223A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263223A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63198324A (en) * | 1987-02-13 | 1988-08-17 | Toshiba Corp | Forming method for pattern |
| JPH01217911A (en) * | 1988-02-25 | 1989-08-31 | Nec Corp | Manufacture of semiconductor device |
-
1985
- 1985-05-17 JP JP60104048A patent/JPS61263223A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63198324A (en) * | 1987-02-13 | 1988-08-17 | Toshiba Corp | Forming method for pattern |
| JPH01217911A (en) * | 1988-02-25 | 1989-08-31 | Nec Corp | Manufacture of semiconductor device |
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