JPS61164254A - Cmoc semiconductor device - Google Patents

Abstract

PURPOSE:To effectively suppress the generation of a latch-up phenomenon by a method wherein an N<+> type contact region to be connected to power source voltage and a P<+> type contact region to be connected to the earth poten tial VSS are arranged on the semiconductor substrate located between the source regions of two MOS transistors and a P-type well region respectively. CONSTITUTION:A P-channel MOS transistor 5, consisting of P<+> type source and drain regions 2 and 3 and a gate electrode, is formed on an N-type semicon ductor substrate 1, and an N<+> type source and drain regions 7 and 8 and an N-channel MOS transistor 10, consisting of a gate electrode 9, are formed on a P-type well region 6. An N<+> type first contact region 11 and a P<+> type second contact region 12 are formed on the semiconductor substrate 1 located between the source regions 2 and 7 of transistors 5 and 10 and the well region 6 respec tively. As the PNP transistor 14, constituting the holding loop of latch-up, and an NPN transistor 15 ar turned to non-conductive state, the latch-up phenome non can be easily prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a CMOS semiconductor device integrated within the same chinobu, and particularly to a CMOS semiconductor device in which a guard region is removed and a latch-up phenomenon is prevented.

(b) In the conventional CMOS semiconductor device, a latch-up phenomenon essentially occurs due to the PNPN structure, which limits the operating range of the CMOS semiconductor device. However, although various layout measures can be considered to suppress this latch-up phenomenon, it is difficult to increase the chip size to suppress the latch-up phenomenon. Therefore, as the miniaturization of elements progresses, it has become very important to take measures against latch-up within a range that does not occupy much area of the chip.

First, conventional CMOS semiconductor devices (for example, Japanese Patent Laid-Open No. 59-1
．． 6365) will be explained with reference to FIG. An N+ type guard region C! is provided on the N type semiconductor substrate (21). A P channel MO8 transistor 06) consisting of P+ type source and drain regions (23) (24) and a gate electrode C51 is formed in a region surrounded by 2+.
A P+ type guard region (N+ type source and drain region (291C30) and gate electrode l31 in the region surrounded by 2) is provided around the P type well region.
An N-channel MO8 transistor C321 is formed. Both MO8 transistors (26) (321
In order to configure the inverter circuit, both drain regions Q4) (
g) and both gate electrodes (25) C3]) are connected, and the source region (c) of the P-channel MO8 transistor (3(i)) and the N+ type guard region (221) are connected and connected to the power supply voltage Vcc. , source region (29) of N-channel #MO8 transistor 0 and P+ type.

The inside of the guard region is connected to the ground potential Lg. Note that the points indicated by black circles in the figure indicate ohmic contacts.

In such a CMOS semiconductor device, as shown in FIG. 4, launch-up occurs between the P+ type source region +231 of the N type semiconductor substrate 01) connected to the power supply voltage cc and the N type of the P type well region (b) connected to the ground potential v0. Source area (2)
between the P+ type source region (c) and the N type semiconductor substrate (2).
+1-PNP transistor (341) composed of P-type well region (c) and N+-type source region Q91-P-type well region G7 -N composed of N-type semiconductor substrate (21)
This occurs when both PN transistors OQ are turned on. Conventionally, in order to prevent the latch-up phenomenon from occurring, an N+ type guard region f22) is provided to reduce the power supply potential V.
0 to prevent potential fluctuations of the N-type semiconductor substrate (21), or provide a P+ type guard region track to connect to the ground potential V Ill.
The potential fluctuation of the P-type well region 07) was suppressed as much as possible. However, the guard region (221+281 power supply potential V
cc or ground potential ■. Guard area C depending on how it is taken.
There was a risk that the parasitic resistances R, , R, of 21 ＼ would form a holding loop and cause latch-up.

4. Problems to be solved by the invention However, as the miniaturization of elements progresses, both MO8 transistors (2G'r (3-effect source region (23) (2!
There is a drawback that when the distance between 1 becomes small, latch-up phenomenon tends to occur.

Further, the provision of the N+ type guard region (22) and the P+ type guard region has the drawback of being a major hindrance to miniaturization of CMOS semiconductor devices.

B) Means for Solving the Problems The present invention has been made in view of these drawbacks, and it eliminates the guard region and connects the N+ type contact region 01) connected to the power supply voltage ccK to the ground potential v. The P+ type contact region 0 connected to the source region of both MO8 transistors (2
P-type well region (6) on the semiconductor substrate Ill between H7)
The object of the present invention is to provide a CMOS semiconductor device that effectively suppresses the occurrence of a latch-up phenomenon by arranging them on top of each other.

01 action In the CMOS semiconductor device according to the present invention, the N+ type contact region Ql+ is connected to the P+ type contact region 021 in the semiconductor substrate (1) between the source regions of both transistors +21F7).
In order to respectively arrange on the P-type well region (6) on the top,
Since the PNP transistor 04) and the NPN transistor a constituting the holding loop of the latch amplifier are no longer conductive, the launch amplifier phenomenon can be easily prevented.

(F) Embodiment A CMOS semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

The CMOS semiconductor device according to the present invention is as shown in FIG.
A P channel MO8 transistor (5) consisting of a P+ type source and drain region (21 (31) and a gate electrode (4) is formed on an N type semiconductor substrate (1), and an N+ type source and drain region is formed on a P type well region (6). Area +71 (
N-channel MO consisting of 81 and gate electrode (9)
8 transistors 00) and both transistors/discs (5)
An N+ type first contact region (11) and a P+ type second contact region a4 are formed in the semiconductor substrate (1) and well region (6) between the source regions (+2117) of Ql, respectively. Both drain regions ta+ts+ and both gate electrodes +41 (91) are connected with a vapor-deposited aluminum electrode layer 031 shown by dotted lines to form an inverter circuit.
The source region (2) of the transistor (5) and the first N+ type
The contact region 01) is connected to the power supply voltage ■cc, and the source region (7) of the N-channel MOS transistor OQ and the P+ type second contact region u21 are connected to the ground potential Vms. . Note that the points indicated by black circles in the figure indicate ohmic contacts.

In the CMOS semiconductor device of the present invention, as shown in FIG.
+-N type semiconductor substrate (1) - PNP transistor 04) consisting of P type well region (6), N+ type source region (P type well region f6) - N type semiconductor substrate f
An NPNI transistor (15) consisting of il is formed. However, the first contact area of N+ type (old)
is provided between both MO8+- transistors (5) (In2), most of the parasitic current from the NPN transistor 051 is sucked out by the first contact region (11), and the PNP
Almost no parasitic current flows between the base and emitter of the transistor (14), and no holding loop is formed due to the internal resistance of the semiconductor substrate (1). Also, the first contact area 01
) and the source region (2) is a vapor-deposited aluminum electrode layer (1
3), there is no parasitic resistance and no holding loop is formed. Furthermore, a P+ type second contact region (12
) is also provided between both MOS transistors (51HJ, so it is PNP).Most of the parasitic current of the run raster 0 is sucked out by the second contact region Q2+ and escapes to the vapor-deposited aluminum electrode layer 03), resulting in an NPN transistor 0.
There is almost no supply to the base of 51. For this reason, NP
The retention loop due to the internal resistance of the well region (6) does not work between the base and emitter of the NI-transistor (1!lil).
) are connected by the vapor-deposited aluminum electrode layer 01 shell, so there is no parasitic resistance and a holding loop is formed.

As is clear from the following, in the CMOS semiconductor device of the present invention, the first contact region circle and the second contact region Q2
The holding loop between the base and emitter of the PNP transistor (1 (a) and NPN transistor (15)) is completely interrupted by the action of +, so that the latch-up strength is greatly improved.

(G) Effects of the Invention According to the present invention, firstly, the N+ type first contact region (I
The latch amplifier phenomenon can be effectively suppressed only by the layout of the ll and P+ type second contact regions Q2), and measures against the latch amplifier can be easily taken.

Second, in the present invention, latch-up strength can be improved without using a guard region, which can greatly contribute to miniaturization of CMOS semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a top view illustrating a CMOS semiconductor device according to the present invention, FIG. 2 is a sectional view illustrating the operating principle of the present invention, FIG. 3 is a top view illustrating a conventional CMOS semiconductor device, and FIG. FIG. 2 is a cross-sectional view illustrating the operation of a conventional latch-up. Explanation of the main drawing numbers: (1) is a semiconductor substrate, (5) is a P-channel MO8) transistor, 00) is an N-channel MO8 transistor,
(II) is the first contact region, (l is the second contact region, Q3) & is the vapor deposited aluminum electrode layer, α is P
NP transistor (151 is an NPN transistor.

Claims (1)

[Claims] (1) MO of one conductivity type semiconductor substrate, opposite conductivity type well region, and one conductivity channel formed on the surface of the semiconductor substrate
In a CMOS semiconductor device comprising an S transistor and a reverse conduction channel MOS transistor formed in the well region, the A first contact region of one conductivity type and a second contact region of the opposite conductivity type are provided on the surface of the semiconductor substrate and the surface of the well region, respectively, and the first contact region and the source region of the MOS transistor of the one conductivity channel are connected by a metal electrode layer. A CMOS semiconductor device, characterized in that the second contact region and the source region of the MOS transistor of the reverse conduction channel are connected by a metal electrode layer and a ground potential is applied.