JPS61164251A - Semiconductor injection integrated logic circuit device - Google Patents

Abstract

PURPOSE:To increase the degree of integration of the titled device by a method wherein a diffusion layer, including an IIL part, and a color region are formed into a double-stage concentration structure. CONSTITUTION:When an N<-> type epitaxial alyer 3 is grown on a P-type silicon semiconductor substrate 1, an N<+> type buried alyer 2 is also formed simultane ously. An oxide film 3a is formed on the surface of the epitaxial layer 3 by heating, the impurities 18 having he concentration lower than that of deposited impurities 17 are deposited on the oxide film 3a surrounded by a hole 16, and then a flat diffusion layer 19 having the concentration a little higher than that of the epitaxial layer and an annular colored region 15 having the concentration a little lower than that of the base region 7, which will be formed by a succeed ing process, are formed by performing a diffusion on the epitaxial layer 3 at the same time when an isolation diffusion process is performed on the impurities 17 and 18. An injection region 6 and a base region 7 are formed on the diffusion layer 19, collectors 8 and 9 are formed on the base region in the same manner as above, and an injection electrode 10, a base electrode 11, the first collector electrode 12 and the second collector electrode 13 are provided on each region.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor implanted integrated logic circuit device (hereinafter referred to as F, IIL).

(b) Conventional technology Two transistors (QI, QR) are placed on one semiconductor substrate.
) is configured as shown in FIG. 2, generally, as shown in FIG. 3, the injection side is a lateral PNP transistor (QI) and the output side is a reverse vertical N P N l
- As a transistor (QR), it has a structure in which the collector of a lateral PNP l-transistor (QI) is shared with the base of a reverse vertical NPN transistor (QR). That is, a type of buried layer (2) is formed on a P-type silicon substrate (1).
), and an N-type epitaxial layer 71 formed by epitaxial growth on the substrate (1)! (3) is separated into islands by P'-shaped separation regions (4) to form island regions (5). This island region (5) has P-type expansion regions (8), (7) and J
: N-type diffusion regions (8) and (9) are sequentially formed by impurity diffusion (7), and electrodes (10) to (14) are provided through electrode holes formed in the oxide film (3a). The lateral P N P l-lancistor (Q+) has the P type diffusion region (6) as the ]-mitter (injector), the epitaxial layer (island region (5)) as the base, and the P type diffusion region (7) as the collector. Works with ground.-Noj reverse vertical NPN
) The transistor (QR) is an epitaxial layer (island region (5
)) is the emitter, the P-type diffusion region (7) is the base, and the N-type diffusion regions (8) and (9) are the collector.

In such IIL, inverted vertical NPN I-
In order to increase the reverse current amplification factor βl of the transistor and obtain high-speed operation, the base region of the reverse vertical NPN transistor is surrounded by an N+ type collar region (15) to suppress the reverse injection of poles. , reverse current increase 1] is known to increase the rate βi.For example,
For details, see Publication No. 030.

(c) Problems to be solved by the invention In the color area (15) of the above-mentioned conventional structure, there is a high concentration of
It is known that when +n diffusion is performed, the emitter IF efficiency increases by -1, and the reverse current increase rate βi can be increased. However, this color region (15) is
Naturally, in order to form a diffusion layer, it must be diffused in the lateral direction, so the collar region (]5) digs into the base region (7) and comes too close to the 7I collector regions (8) and (9), causing collector and emitter regions. This often causes poor pressure resistance.

In particular, this defect is often caused by mask misalignment when forming diffusion holes for diffusing the collar region (15) in the oxide film by photoetching/etching.

In order to prevent this defect from occurring, conventionally it was necessary to make a certain amount of space between the high-density color area 15) and the base area (7), which was an obstacle to increasing the degree of integration. In order to solve this problem, the applicant has proposed that the diffusion layer containing the IIL portion and the oak region have a two-layer structure, which increases the number of manufacturing steps. The object of the present invention is to provide a manufacturing method that allows a two-layer structure to be formed without causing any damage.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned conventional problems. a buried layer of opposite conductivity type inserted between the substrate and the layer, a low concentration reverse conductivity type diffusion layer in which -C is diffused from the surface of the epitaxial layer toward the buried layer, and adjacent to the inside of the diffusion layer. an injector region and a base region of one conductivity type; a collector region of an opposite conductivity type provided on the surface of the base region; and a collar region of an opposite conductivity type within the diffusion layer and surrounding the base region and the injector region. In order to suppress the increase in process steps when manufacturing a device having a structure in which the surface concentration of the color region is slightly lower than that of the base region, the diffusion process for forming the diffusion layer and the color region is separated from the diffusion process. It is characterized by a method of simultaneously diffusing into the epitaxial layer.

(Po) Function According to the present invention, since the IIL section is provided in the low-concentration deep N-type diffusion layer, the current increase rate of the IIL section is increased while maintaining the breakdown voltage of the linear section, and the surface concentration of the color region is increased. The spacing between the color area and the base area is set to a level slightly lower than the surface concentration of the base area, and even if the lateral diffusion during diffusion comes into contact with the base area, the base area does not substantially bite into the base area, so the distance between the color area and the base area is This makes it possible to narrow the area and increase the degree of device integration.”
- It is possible to prevent the reverse current amplification factor β1 from decreasing and to stabilize the process and improve the yield without causing an increase in the number of manufacturing steps.

(F) Embodiment FIG. 1 is a sectional view showing an IIL according to the present invention in the order of manufacturing steps.

First, N-type impurities are densely deposited in the center of the second surface of a P-type silicon semiconductor substrate (1), and then an N-type epitaxial layer (3) is grown on the substrate (1).
An N+ type buried layer (2) inherent in both the epitaxial layer and the epitaxial layer is formed at the same time. FIG. 1(a), then heated in an oxidizing atmosphere furnace to form an oxide film (3a) on the surface of the C epitaxial layer (3), and as shown in FIG. 1(b), the oxide film (3a)
A hole (16) is formed by photoetching at a position surrounding the base region (7) to be formed in a later process, and a relatively narrow concentration of N4 type impurity (17) is implanted in the above-mentioned shrimp layer exposed through the hole. 1(C), an oxide film (3a) surrounding the hole (16)
Then, the impurity (18) with a concentration lower than that of the deposited impurity (17) is deposited on the epitaxial layer exposed by L etching (Fig. 1(d)), and then the deposited impurity ( 17〉 (18) is separated and diffused into the corpitachine layer (3) at the same time as the flattened diffusion layer (19) whose concentration is slightly higher than the concentration of the corpitachine layer (19) in the subsequent process. 11 annular color regions (15) are formed at a concentration lower in N than the Hose region (7) to be formed.
This refers to the process of forming an island region (4.9) around the entire ITL region in a ring shape with a P-type region in order to make each part independent), and exposing it except for the oxide film in the desired region. This is a step in which P-type impurities are deposited on the bitaxeal layer and then heated. Figure 1 (r>kl Heating means after oxide film removal and impurity deposition C1 diffusion layer <J9) injector area (6)
Figure 1 (g) shows the state in which the base region (7) is formed.
) is added to the base area in the same way as =l[・kuku(8)(9)
Figure 1(i) shows the state in which the injected electrodes (1) are formed with ohmic contacts in each region.
0), Base V, Pole (11), 1st Koku electrode (1
2) A second collector M pole (13) is installed (J shows the completed state of the device of the present invention.

(1.) Effects of the Invention According to the present invention, the diffusion layer and the color region, which include the ITL region, have a two-layer structure, that is, the concentration of one of the layers can be increased while maintaining the breakdown voltage of the linear region. forward type dL of
In addition, the surface concentration of the color region is kept high even if the color region is closer to the base region. There is no encroachment on the area (!) When setting x1, the base area and color area can be brought closer together than in the conventional structure, increasing the degree of integration (').

As shown in the example, the manufacturing of the two-layer composite structure that achieves this effect involves forming the diffusion layer and the color region simultaneously in a separate diffusion process, which requires no additional steps compared to the conventional manufacturing process. Not accompanied.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the 35 manufacturing methods of the present invention in the order of E steps, v
The Jz diagram is a circuit diagram of the IIL, and FIG. 3 is a sectional view showing the conventional ■IL structure. (1) Semiconductor substrate, (2) Buried layer, (3)
Ebikugishiheru layer, (6), injector region, (7
)・Base area, (8), (9) ・Collector area,
(15)...Color area, (19)...Diffusion layer.

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor implanted integrated logic circuit device comprising the following steps. a. A step of growing an epitaxial layer of an opposite conductivity type by including a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type; b. A step of providing an oxide film on the surface of the epitaxial layer; c. The oxide film. forming a hole at a position surrounding a base region to be formed in a later step, and depositing a relatively high concentration of impurity of the opposite conductivity type on the epitaxial layer through the hole; d. removing the oxide film surrounded by the hole; and depositing an opposite conductivity type impurity in the exposed epitaxial layer at a concentration lower than that of the deposited impurity, e. Diffusing the deposited impurity into the epitaxial layer at the same time as the separation and diffusion step so as to have a concentration slightly higher than that of the epitaxial layer. f. forming an annular color region with a slightly lower density than a base region formed in a subsequent step; f) forming an injector region and a base region in the diffusion layer; g. forming a collector in the base region;