JPS61160967A - Semiconductor injection integrated logic circuit device - Google Patents
Semiconductor injection integrated logic circuit deviceInfo
- Publication number
- JPS61160967A JPS61160967A JP60001753A JP175385A JPS61160967A JP S61160967 A JPS61160967 A JP S61160967A JP 60001753 A JP60001753 A JP 60001753A JP 175385 A JP175385 A JP 175385A JP S61160967 A JPS61160967 A JP S61160967A
- Authority
- JP
- Japan
- Prior art keywords
- region
- concentration
- base region
- layer
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000002347 injection Methods 0.000 title abstract description 7
- 239000007924 injection Substances 0.000 title abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000003321 amplification Effects 0.000 abstract description 9
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体注入集積論理回路装置（以下、ＩＩＬと
いう、）に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor implanted integrated logic circuit device (hereinafter referred to as IIL).
（ロ） 従来の技術
一つの半導体基板上に二つのトランジスタ（Ｑ＋、Ｑｉ
）を第２図に示″すように構成されたＩＩＬは、一般に
第３図に示すように、注入側をラテラルＰＮＰトランジ
スタ（Ｑりとし、出力側を逆方向縦形ＮＰＮｈランジス
タ（ＱＲ）として、ラテラルＰＮＰトランジスタ（Ｑり
のコレクタを゛逆方向縦形ＮＰＮトランジス゛り＜Ｑｓ
ｒ）のベースと共用する構造を有する。すなわち、Ｐ型
シリコン基板（１）上にＮ０型の埋め込み層（２）を設
け、基板（１）上にエピタキシャル成長で形成されたＮ
−型のエピタキシャル層く３）をＰ゛型の分離領域（４
）で島状に分離して島領域（５）が形成きれる。この島
領域（５）にＰ型拡散領域（６）（７）およびＮ型拡散
領域（８）（９）を順次不純物拡散によって形成し、酸
化膜（３ａ）に設けた電極孔を介して電極（１０）〜（
１４）が設けられている。そしてラテラルＰＮＰ ｌ−
ランジスタ（Ｑｌ）はＰ型拡散領域（６〉がエミッタ（
インジェクタ）、エピタキシャル層（島領域（５））が
ベース、Ｐ型拡散領域（７）がコレクタでベース接地で
働く、一方逆方向縦形ＮＰＮトランジスタ（Ｑｉ）はエ
ピタキシャル層（島領域（５））がエミッタ、Ｐ型拡散
領域（７）がベース、Ｎ型拡散領域（８）（９）がコレ
クタとなっている。(b) Conventional technology Two transistors (Q+, Qi
) is configured as shown in FIG. 2, generally, as shown in FIG. 3, the injection side is a lateral PNP transistor (Q) and the output side is a reverse vertical NPNh transistor (QR). Lateral PNP transistor (reverse direction vertical NPN transistor with collector of Q<Qs
It has a structure that is shared with the base of r). That is, an N0-type buried layer (2) is provided on a P-type silicon substrate (1), and an N0-type buried layer (2) is formed on the substrate (1) by epitaxial growth.
- type epitaxial layer 3) and P-type isolation region (4).
) to form island regions (5). P-type diffusion regions (6) (7) and N-type diffusion regions (8) (9) are sequentially formed in this island region (5) by impurity diffusion, and electrodes are formed through the electrode holes provided in the oxide film (3a). (10)～(
14) is provided. and lateral PNP l−
The transistor (Ql) has a P-type diffusion region (6〉) as an emitter (
Injector), the epitaxial layer (island region (5)) is the base, and the P-type diffusion region (7) is the collector, and the base is grounded. The emitter, the P-type diffusion region (7) serves as the base, and the N-type diffusion regions (8) and (9) serve as the collector.
このようなＩＩＬにおいては、逆方向縦形ＮＰＮトラン
ジスタの逆方向電流増巾率βｌを高くして高速動作を得
るために、逆方向縦形ＮＰＮ トランシスタノベース領
域をＮ゛型のカラー領域（１５）で取り囲んでホールの
逆注入を抑制して、逆方向電流増巾率βｉを高くするこ
とが知られている６例えば、特公昭４９−３５０３０号
公報に詳しい。In such IIL, in order to increase the reverse current amplification factor βl of the reverse vertical NPN transistor and obtain high-speed operation, the reverse vertical NPN transistor base region is formed with an N-type collar region (15). It is known that the reverse injection of holes is suppressed by surrounding the holes, thereby increasing the reverse current amplification factor βi.
（ハ） 発明が解決しようとする問題点前述の従来構造
のカラー領域（１５）に高濃度の深いｎ拡散を行うとエ
ミッタ注入効率が向上し、逆方向電流増巾率βｉを高く
出来ることが知られている。しかし、このカラー領域（
１５）を高濃度の深いｎ拡散層とするには当然その横方
向拡散が伴なうため、カラー領域（１５）がベース領域
（７）に喰い込みコレクタ領域（８）（９）に接近しす
ぎてコレクタ、エミッタ耐圧不良の原因となることが多
い。(c) Problems to be Solved by the Invention It is possible to improve the emitter injection efficiency and increase the reverse current amplification factor βi by performing deep n-diffusion at a high concentration in the collar region (15) of the conventional structure described above. Are known. However, this color region (
15) to form a deep n-diffused layer with high concentration naturally involves its lateral diffusion, so the collar region (15) digs into the base region (7) and approaches the collector regions (8) and (9). Too much voltage often causes collector and emitter breakdown voltage failure.
特にこの不良は酸化膜にカラー領域（１５）を拡散させ
る拡散孔をホトエツチングで設ける際のマスクずれによ
る場合が多い。In particular, this defect is often caused by mask misalignment when photo-etching a diffusion hole for diffusing the collar region (15) into the oxide film.
この不良発生を紡ぐため、従来は高濃度のカラー領域（
１５）とベース領域（７）の間をある程度広くとらざる
を得なかった為に集積度を上げる際の障害となっていた
。In order to solve this problem, conventionally, high-density color areas (
15) and the base area (7), which was an obstacle to increasing the degree of integration.
（ニ） 問題点を解決するための手段本発明は上述し
た従来の問題点を解決すべくなされたもので、一導電型
の半導体基板、該板上に形成される逆導電型のエピタキ
シャル層、前記基板と前記層間に挿入される逆導電型の
埋め込み層、前記エピタキシャル層の表面より埋め込み
層に向けて拡散させた低濃度の逆導電型拡散層、前記拡
散層内に隣接して設けた一導電型のインジェクタ領域及
びベース領域、前記ベース領域表面に少なくとも一つ設
けられる逆導電型のコレクタ領域と前記拡散層内で且前
記ベース領域およびインジェクタ領域を囲む逆導電型の
カラー領域からなり、前記カラー領域の表面濃度をベー
ス領域の表面濃度よりやへ低くした事を特徴とする。(d) Means for solving the problems The present invention was made to solve the above-mentioned conventional problems, and includes a semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type formed on the substrate, a buried layer of opposite conductivity type inserted between the substrate and the layer; a low concentration diffusion layer of opposite conductivity type diffused from the surface of the epitaxial layer toward the buried layer; an injector region and a base region of a conductivity type, a collector region of an opposite conductivity type provided at least one on the surface of the base region, and a collar region of an opposite conductivity type within the diffusion layer and surrounding the base region and the injector region; It is characterized in that the surface density of the color area is slightly lower than that of the base area.
（ホ） 作用
本発明によれば、低濃度の深いＮ型拡散層にＩＩＬ部を
設けるのでリニア部の耐圧を保ちなからＩＩＬ部の電流
増巾率を高め更にカラー領域の表面濃度をベース領域の
表面濃度よりゃへ低い程度としたへめ、拡散時の横方向
拡散がベース領域に接したとしても実質的にはベース領
域の喰い込みが生じないのでカラー領域とベース領域と
の間隔を狭める事が可能となり素子の集積度を向上きせ
るとともに逆方向電流増巾率βｉの低下も防ぎ工程の安
定化及び歩留の向上が計れる。(E) Function According to the present invention, since the IIL portion is provided in the low concentration deep N-type diffusion layer, the withstand voltage of the linear portion is maintained, the current amplification rate of the IIL portion is increased, and the surface concentration of the color region is increased to the base region. The spacing between the color area and the base area should be narrowed because even if the lateral diffusion during diffusion touches the base area, the base area will not actually be eaten away. This makes it possible to improve the degree of integration of the device and also prevent a decrease in the reverse current amplification factor βi, thereby stabilizing the process and improving yield.
（へ）実施例
第１図は本発明によるＩＩＬの原理的構造を断面図にて
示すものである。同図に示されるＩＩＬはＰ型のシリコ
ン半導体基板（１）とその基板（１）上にエピタキシャ
ル成長させたＮ−型のエピタキシャル層（３〉との間に
Ｎ゛型の埋め込み層（２）が設けられる。 （１６）は
前記エピタキシャル層〈３）表面から埋め込み層（２）
に向けて燐の不純物を拡散きせて設けた低濃度のＮ゛型
型数散層（６）（７）は前記拡散層（１６）に設けたＰ
型のインジェクタ領域及びベース領域、（８）（９）は
前記ベース領域（７）に設けたコレクタ領域、（１５）
は前記拡散層（１６）内で且前記ベース領域（７）及び
インジェクタ領域を囲むＮ０型のカラー領域で、該領域
（１５）の表面濃度をベース領域（７）の表面濃度より
や〜低く設定しである。ちなみに拡散層の濃度はベース
領域に比べ充分低い。(F) Embodiment FIG. 1 is a sectional view showing the basic structure of an IIL according to the present invention. The IIL shown in the figure has an N-type buried layer (2) between a P-type silicon semiconductor substrate (1) and an N-type epitaxial layer (3) epitaxially grown on the substrate (1). (16) is the buried layer (2) from the surface of the epitaxial layer (3).
The low-concentration N-type scattering layers (6) and (7) are provided by diffusing phosphorus impurities toward the P diffusion layer (16).
An injector area and a base area of the mold, (8) and (9) a collector area provided in the base area (7), (15)
is an N0 type color region within the diffusion layer (16) and surrounding the base region (7) and the injector region, and the surface concentration of the region (15) is set to be slightly lower than the surface concentration of the base region (7). It is. Incidentally, the concentration of the diffusion layer is sufficiently lower than that of the base region.
（１０）（１１）（１２）（１３）はエピタキシャル層
（３）表面に設けられた酸化膜（３ａ）上番こ開けた電
極孔を介して各領域にオーミックコンタクトした電極で
夫々インジェクタ電極、ベース電極、第１フレクタ電極
、第２フレクタ電極を構成する。なお、拡散層内に構成
される逆方向縦形ＮＰＮトランジスタのエミッタ電極（
１４）はカラー領域（１５）にオーミックコンタクトす
ることにより電極の取り出しが行われる。(10), (11), (12), and (13) are electrodes that are in ohmic contact with each region through electrode holes made in the upper part of the oxide film (3a) provided on the surface of the epitaxial layer (3). A base electrode, a first flexor electrode, and a second flexor electrode are configured. Note that the emitter electrode (
14), the electrode is taken out by making ohmic contact with the collar region (15).
本発明の特徴は第１図に示すように、ベース領域（７）
を囲む領域がベース領域（７）の表面濃度よりや〜低い
濃度と充分低い濃度の２段の濃度構造を形成する事で、
リニア部の耐圧を高め且ＩＩＬ部のエミッタ注入効率を
向上させ逆方向ｉＥ流増巾率を高めている。The feature of the present invention is that, as shown in FIG.
By forming a two-stage concentration structure in which the region surrounding the base region (7) has a slightly lower concentration and a sufficiently lower concentration than the surface concentration of the base region (7),
The breakdown voltage of the linear section is increased, the emitter injection efficiency of the IIL section is improved, and the reverse iE flow amplification rate is increased.
（ト）発明の効果
本発明によれば、ＩＩＬ部を含む事になる拡散層とカラ
ー領域が、２段濃度構造となるから即ち一方の濃度はリ
ニア部の耐圧を保ちながらＩＩＬ部の順方向電流増巾率
に高く保ち、更に他方の濃度でＩＩＬ部の逆方向エミッ
タ注入効率の向上に役立つ、加えてカラー領域の表面濃
度はたとえカラー領域がベース領域により接近してもベ
ース領域を喰い込む事がないので、設計時にベース領域
とカラー領域を従来構造より更に接近させる事ができる
ので集積度を上げる。(G) Effects of the Invention According to the present invention, the diffusion layer and the color region that include the IIL part have a two-stage concentration structure, that is, one concentration is applied in the forward direction of the IIL part while maintaining the withstand voltage of the linear part. The current amplification factor is kept high, and the other concentration helps to improve the reverse emitter injection efficiency of the IIL section.In addition, the surface concentration of the collar region digs into the base region even if the collar region is closer to the base region. Therefore, during design, the base area and color area can be brought closer together than in the conventional structure, increasing the degree of integration.
第１図は本発明によるＩＩＬ（７）原理的構造を示す断
面図、第２図はＩＩＬの回路図、第３１には従来のＩＩ
Ｌ構造を示す断面図である。
（１）・・・半導体基板、（２）・・・埋め込み層、（
３）・・・エピタキシャル層、（６）・・インジェクタ
領域、（７）・・・ベース領域、（幻、（９）・・・コ
レクタ領域、（１６）・・・拡散層。Fig. 1 is a sectional view showing the basic structure of IIL (7) according to the present invention, Fig. 2 is a circuit diagram of IIL, and Fig. 31 is a conventional IIL (7).
It is a sectional view showing an L structure. (1)...Semiconductor substrate, (2)...Buried layer, (
3)...Epitaxial layer, (6)...Injector region, (7)...Base region, (phantom, (9)...Collector region, (16)...Diffusion layer.
Claims (1)
電型のエピタキシャル層、前記基板と前記層間に挿入さ
れる逆導電型の埋め込み層、前記エピタキシャル層の表
面より埋め込み層に向けて拡散させた低濃度の逆導電型
拡散層、前記拡散層内に隣接して設けた一導電型のイン
ジェクタ領域及びベース領域、前記ベース領域表面に少
なくとも一つ設けられる逆導電型のコレクタ領域と前記
拡散層内で且前記ベース領域およびインジェクタ領域を
囲む逆導電型のカラー領域からなり、前記カラー領域の
表面濃度をベース領域の表面濃度よりやゝ低くした事を
特徴とする半導体注入集積論理回路装置。(1) A semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type formed on the substrate, a buried layer of the opposite conductivity type inserted between the substrate and the layer, and a direction toward the buried layer from the surface of the epitaxial layer. an injector region and a base region of one conductivity type provided adjacent to the diffusion layer, a collector region of the opposite conductivity type provided at least one on the surface of the base region; A semiconductor implanted integrated logic circuit comprising a collar region of opposite conductivity type within the diffusion layer and surrounding the base region and the injector region, the surface concentration of the collar region being slightly lower than the surface concentration of the base region. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001753A JPS61160967A (en) | 1985-01-09 | 1985-01-09 | Semiconductor injection integrated logic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001753A JPS61160967A (en) | 1985-01-09 | 1985-01-09 | Semiconductor injection integrated logic circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61160967A true JPS61160967A (en) | 1986-07-21 |
Family
ID=11510333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60001753A Pending JPS61160967A (en) | 1985-01-09 | 1985-01-09 | Semiconductor injection integrated logic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61160967A (en) |
-
1985
- 1985-01-09 JP JP60001753A patent/JPS61160967A/en active Pending
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