JPS6116093B2 - - Google Patents

Info

Publication number
JPS6116093B2
JPS6116093B2 JP55059018A JP5901880A JPS6116093B2 JP S6116093 B2 JPS6116093 B2 JP S6116093B2 JP 55059018 A JP55059018 A JP 55059018A JP 5901880 A JP5901880 A JP 5901880A JP S6116093 B2 JPS6116093 B2 JP S6116093B2
Authority
JP
Japan
Prior art keywords
data
input
output
shift
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55059018A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56155444A (en
Inventor
Osamu Nishijima
Makoto Yamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP5901880A priority Critical patent/JPS56155444A/ja
Publication of JPS56155444A publication Critical patent/JPS56155444A/ja
Publication of JPS6116093B2 publication Critical patent/JPS6116093B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Shift Register Type Memory (AREA)
JP5901880A 1980-05-02 1980-05-02 Large scale integrated circuit device Granted JPS56155444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5901880A JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5901880A JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Publications (2)

Publication Number Publication Date
JPS56155444A JPS56155444A (en) 1981-12-01
JPS6116093B2 true JPS6116093B2 (enrdf_load_stackoverflow) 1986-04-28

Family

ID=13101122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5901880A Granted JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Country Status (1)

Country Link
JP (1) JPS56155444A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143285A (ja) * 1991-11-20 1993-06-11 Matsushita Electric Ind Co Ltd 演算装置

Also Published As

Publication number Publication date
JPS56155444A (en) 1981-12-01

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