JPS61159746A - Icモジユ−ルのワイヤボンデイング方法 - Google Patents

Icモジユ−ルのワイヤボンデイング方法

Info

Publication number
JPS61159746A
JPS61159746A JP60000365A JP36585A JPS61159746A JP S61159746 A JPS61159746 A JP S61159746A JP 60000365 A JP60000365 A JP 60000365A JP 36585 A JP36585 A JP 36585A JP S61159746 A JPS61159746 A JP S61159746A
Authority
JP
Japan
Prior art keywords
bonding
wire
module
pad
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60000365A
Other languages
English (en)
Inventor
Koichi Ueno
浩一 上野
Masao Muramatsu
村松 正男
Yoshihiko Nakahara
中原 義彦
Toshio Haga
芳賀 敏夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyodo Printing Co Ltd
Original Assignee
Kyodo Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyodo Printing Co Ltd filed Critical Kyodo Printing Co Ltd
Priority to JP60000365A priority Critical patent/JPS61159746A/ja
Publication of JPS61159746A publication Critical patent/JPS61159746A/ja
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/85051Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICモジュールを組立てる際の、ICチップ
のパッドと基板上のリードとの間のワイヤボンディング
方法に関するものである。
〔従来技術〕
ICチップと基板との間の配線接続で最も偉績性のある
のは、金線によるネールへラドボンディングである。
〔発明が解決しようとする問題点〕
ネールへラドボンディングに当たっては、先端のボール
をつぶしたネックの部分が塑性変形による歪みのために
断線し易いので、ワイヤを横に引っ張る前に先ず垂直に
立ち上げる必要がある0例えば第2図において、基板l
上に装着されたICチップ2のパッド3と、基板1上の
り一ド4とをワイヤ5によりワイヤボンドする場合、先
ずパッド3上にボールを圧着して第1ボンディング6を
行い、高さh+の垂直な立ち上がり部7を形成した後、
ボンディングツールを横にも移動せしめ、次に下降して
リード4の上に第2ボンディング8を行い、その後ワイ
ヤ端を切断して一組の接続を行う。
このとき、立ち上がり部7の高さり、は180μm−1
000μmを要し、ワイヤ5の最高点までの高さh8が
大となり、カードの厚さに対する規格値0.76mmよ
りも全体の高さHが高くなることがあり、ICモジュー
ルをクレジットカードなどのICカードに組み込むのが
困難な場合がある、という問題点を有するもめであった
本発明は、従来のものの上記のM8点を解決し、ネール
へラドボンディングを用いたICモジュールのボンディ
ングワイヤを含めた総高さを小となし、携帯カードへの
組み込みを容易となし、信頼性の高いICモジュールを
提供することを目的とするものである。
c問題点を解決するための手段〕 本発明は、問題点を解決するための手段として、ICモ
ジュールの、ICチップ上のパッドと、基板上のリード
との間のネールヘッド式ワイヤボンドを行う方法におい
て、先ず前記リード上に第1ボンディングを行った後、
前記パッド上に第2ボンディングを行ってワイヤ接続を
行うことを特徴とするICモジュールのワイヤボンディ
ング方法を提供せんとするものである。
〔実施例〕
本発明の実施例を第1図により説明する。
基板1、ICチップ2、パッド3、リード4の配置は第
2図のものと同様であるが、ボンディング作業に当たっ
ては、第2図の場合とは逆に先ず、リード4上にボール
を圧着して第1ポンデイング6を行った後、所定の高さ
hlの立ち上がり部7を形成し、その後横の方向にも移
動せしめ、次にパッド3の上に第2ボンディング8を行
う。
ネールへラドボンディングの場合は前述の如(はぼ垂直
な立ち上がり部7を形成する必要があるが、第2ボンデ
ィング8においてはキャピラリの先端によりボンド部分
の横方向の部分がつぶされるので、パッド3の表面のボ
ンディング点にキャピラリ先端を近づけるのに、垂直方
向の立ち下がり部は殆ど必要とせず、斜め方向から近づ
けることができる。
第1ボンディング6を行うリード4例のワイヤ5の立ち
上がり部7の高さhl及びワイヤの最高点までの高さり
、は第2図の如き従来のものと同様であるが、通常リー
ド4の表面は、パッド3の表面よりもほぼICチップ2
の厚さ分(通常300〜500μm)程度低くなってい
るので高さhよは同様であっても全体の高さHは、従来
のものに比べて300〜500μm程度低くすることが
でき、ICモジュールの総厚への影響を最小限にするこ
とができる。従ってネールへラドボンディングを適用し
、なおかつICカードの薄型化を極めて容易に行うこと
ができる0例えば従来1mm近くであった厚さを0.6
mm以下とすゐことが容易となった。
〔発明の効果〕
本発明により、薄さが要求されるICカードのICモジ
ュールのワイヤボンディングに対し、ネールへラドボン
ディングを適用することが可能となり、ICモジュール
のボンディングの信頼性が大であり、かつ厚さが極めて
薄いrCカードの実現を可能とするICモジュールのワ
イヤボンディング方法を提供することができ、実用上極
めて大なる効果を奏する。
【図面の簡単な説明】
第1図は本発明の実施例の断面図、第2図は従来例の断
面図である。 1−・一基板、2−I Cチップ、3−・パッド、4−
リード、5〜・−ワイヤ、6−第1ボンディング、7−
・−立ち上がり部、8−・−第2ボンディング。 特許出願人   共同印刷株式会社 代理人弁理士  高 木  正 行 間   薬師  稔

Claims (1)

    【特許請求の範囲】
  1. 1、ICモジュールの、ICチップ上のパッドと、基板
    上のリードとの間のネールヘッド式ワイヤボンドを行う
    方法において、先ず前記リード上に第1ボンディングを
    行った後、前記パッド上に第2ボンディングを行ってワ
    イヤ接続を行うことを特徴とするICモジュールのワイ
    ヤボンディング方法。
JP60000365A 1985-01-08 1985-01-08 Icモジユ−ルのワイヤボンデイング方法 Pending JPS61159746A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60000365A JPS61159746A (ja) 1985-01-08 1985-01-08 Icモジユ−ルのワイヤボンデイング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60000365A JPS61159746A (ja) 1985-01-08 1985-01-08 Icモジユ−ルのワイヤボンデイング方法

Publications (1)

Publication Number Publication Date
JPS61159746A true JPS61159746A (ja) 1986-07-19

Family

ID=11471764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60000365A Pending JPS61159746A (ja) 1985-01-08 1985-01-08 Icモジユ−ルのワイヤボンデイング方法

Country Status (1)

Country Link
JP (1) JPS61159746A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219131A (ja) * 1987-03-06 1988-09-12 Nec Yamagata Ltd 半導体装置の製造方法
JPS63197362U (ja) * 1987-06-08 1988-12-19
JPS6430834U (ja) * 1987-08-19 1989-02-27
JPH0462024U (ja) * 1990-10-02 1992-05-27
WO2004105133A1 (en) * 2003-05-26 2004-12-02 Axalto Sa Wire bonding on in-line connection pads
EP1321979A3 (en) * 2001-12-03 2005-10-12 Sharp Kabushiki Kaisha Semiconductor module with increased reliability against heavy environment conditions and production method therefor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219131A (ja) * 1987-03-06 1988-09-12 Nec Yamagata Ltd 半導体装置の製造方法
JPS63197362U (ja) * 1987-06-08 1988-12-19
JPH0651001Y2 (ja) * 1987-06-08 1994-12-21 日本電気株式会社 光結合素子
JPS6430834U (ja) * 1987-08-19 1989-02-27
JPH0462024U (ja) * 1990-10-02 1992-05-27
EP1321979A3 (en) * 2001-12-03 2005-10-12 Sharp Kabushiki Kaisha Semiconductor module with increased reliability against heavy environment conditions and production method therefor
WO2004105133A1 (en) * 2003-05-26 2004-12-02 Axalto Sa Wire bonding on in-line connection pads

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