JPS61157114A - Output circuit - Google Patents

Abstract

PURPOSE:To bring an output high level to a power voltage level without causing latch up even when an abnormal noise is applied to the output by constituting the output circuit with the 1st conduction type 1st transistor (TR) whose source is connected to the 1st power supply, the 2nd conductor type 2nd-6th TRs whose sources are connected to the 2nd power supply, a delay circuit and a static capacitor. CONSTITUTION:When the level of an input terminal IN changes from a high level to a low level at a time t1, a TRQ3 is turned on, the 1st contact 1 goes to a high level, then the 3rd and 4th TRS Q5, Q7 are turned on and the 2nd contact 2 and an output terminal OUT go to a high level. However, the high level of the 2nd contact 2 is VCC-VTH and the high level of the output terminal OUT is VCC-2VTH, where VTH is a threshold voltage of TRs. A static capacitor C is charged during this time. When a contact 3 at the output terminal of a delay circuit 4 goes to a high level at a time t2, the high level of the 2nd contact 2 is boosted to a value VCC+VTH or over by the coupling of the capacitor C and the high level of the output terminal OUT goes to the VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an output circuit, and particularly to an output circuit composed of a 0M08 circuit.
'L order output output circuit.

(Prior art) Conventionally, although the manufacturing process is complicated, the 0M08 circuit has the advantages of low power consumption and wide power supply operation margin, so the 0M08 circuit has been used in many integrated circuits. It is made.

(Problems to be Solved by the Invention) In the 0MO8 circuit, when abnormal noise is applied to the input/output terminals, latch-up, which is unique to the 0MO8 circuit, will occur.9th, measures should be taken to prevent the addition of abnormal noise. I rarely needed it.

FIG. 4 is a circuit diagram of an example of a ratio output circuit using a conventional 0M08 circuit, and FIG. 5 is a schematic diagram illustrating latch-up of the output circuit shown in FIG. 4.

A P type semiconductor substrate 11KN well 12t is formed, P diffusion regions 16 and 17 are formed in the N well 12, and a source
The drain region and the gate 20 constitute an N-channel transistor Q2. N in areas other than N Fell 12
Diffusion regions 13 and 14t are formed to serve as source/drain regions, and together with a gate 19 constitute a P-channel transistor Q2.

With this configuration, as shown in the figure, the parasitic NPN
Transistors 'I', , 'I' and parasitic PNP transistors T8 and T4 are formed.

Now, when noise greater than VCC + VF (forward voltage of PN junction) is added to the output, current flows from the output to Nfer 2, turns on the parasitic PNP transistor T3, and current flows from the output to the substrate l, lowering the substrate level. float. When the substrate level rises, the parasitic NPN transistor T2 turns on, current flows from 5Vcc to GND, and the N-well potential drops. Parasitic PNP when the N-well potential decreases? The transistor state 4 is turned on and current flows from VCC to the board, further raising the board level.

In this way, once the NPN transistor T2 and the parasitic P
NP) When transistor T4 is turned on, it is added to the output, and even if the noise disappears, current continues to flow from VCC to GND, causing latch-up.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit that does not cause latch-up even when abnormal noise is applied to the output, and whose output high level becomes the power supply voltage level.

(Means for Solving the Problems) The output circuit of the present invention includes a tenth transistor of a tenth conductivity type in which the drain is connected to a tenth contact, the gate is connected to an input terminal, and the source is connected to a tenth power supply; Connect the gate to the input terminal and the source to the second power supply to the 10th contact 7? , a second transistor of a second conductivity type, a third transistor of a second conductivity type, the drain of which is connected to the tenth power supply, the gate of which is connected to the tenth contact, and the source of which is connected to the second contact; A fourth conductor of the second conductor has a gate connected to the second contact, an input terminal, and a north connected to the second power supply.
a transistor, a drain/gate t to the tenth power supply;
- a fifth transistor of a second conductivity type having a source connected to the second contact and an output terminal; a second transistor having a drain connected to the output terminal, a gate connected to the input terminal, and a source connected to the second power supply;
a delay circuit having an input end connected to the second contact and an output end connected to the third contact; one terminal connected to the second contact and the other terminal connected to the third contact; and a capacitance connected to the capacitor.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, the drain is connected to the tenth contact l, the gate is connected to the input terminal IN, the source is connected to the tenth power supply VCC, and the first transistor Q3 is a 2p channel.
Connect the gate to the contact l and the source to the input terminal IN to the second power supply G.
A second N-channel transistor Q4 connected to ND, a drain connected to the 10th power supply VCC, and a gate connected to the 10th contact l.
, a third transistor Qs of 7tN channel with its source connected to the second contact 2, its drain connected to the second contact 2, its gate connected to the input terminal IN, and its source connected to the second power supply GND, 7'tN. The fourth transistor Q6 of the channel, the drain connected to the 10th power supply vccs, the gate connected to the second contact 2, and the source connected to the output terminal OUT, and the fifth transistor Q6 of the 7tN channel/channel.
A transistor Q7, a sixth N-channel transistor Q8 whose drain is connected to the output terminal OUT, whose gate is connected to the input terminal IN, and whose source is connected to the second power supply GND, whose input terminal is connected to the second contact 2 and whose output terminal is connected to the third A delay circuit 4 is connected to the contact 3, one terminal is connected to the second contact 2, and the other terminal is connected to the third contact.
and a specific capacitance.

FIG. 2 is a detailed circuit diagram of the delay circuit shown in FIG. 1. This circuit uses a P-channel transistor Q.

Q 11 , N-channel/channel transistor Qxo, Qu
7′? , consists of two stages of inverters. The number of inverters is not limited to two stages, but may be an even number of stages. Using an even number of stages of inverters has the advantage that the delay circuit can be easily constructed.

Next, the operation of this embodiment will be explained.

FIG. 3 is an operational waveform diagram of the embodiment shown in FIG. 1.

When the input terminal IN changes from a high level to a low level at time t1, the transistor Qs is turned on and the tenth contact 1 goes to a high level, and the third contact 1 changes from a high level to a low level. Fourth transistor Qs
, Qy are turned on, and the second contact 2° output terminal OUT becomes high level. However, the high level of the second contact 2 is V
CC knee vT Hs The high level of the output terminal OUT is vcc-2VTR.

VTR represents the threshold voltage of a transistor.

During this time, the capacitance C is charged. Next, when the output terminal (contact 3) of the delay circuit 4 becomes high level at time t2, the high level of the second contact 2 rises above (VCC+VTR) due to the coupling of the capacitance C, and the output terminal The high level of OUT becomes VCC. When the input terminal IN changes from low level to high level at time t3, transistor Q
4. Q6. QB turns on, contact 1, second contact 2. The output terminal OUT is reset to low level.

In the above embodiment, the first conductivity type is P type and the second conductivity type is N type, but it goes without saying that the present invention can also be applied to the case where the first conductivity type is N type and the second conductivity type is P type. be.

(Effects of the Invention) As explained above, according to the present invention, since the output stage is composed of transistors of the second conductivity type, latch-up does not occur even if abnormal noise is added to the output. An output circuit is obtained in which the high level at the output terminal becomes the VCC level.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a detailed circuit diagram of the delay circuit shown in Fig. 1, Fig. 3 is an operation waveform diagram of the embodiment shown in Fig. 1, and Fig. 4 is a detailed circuit diagram of the delay circuit shown in Fig. FIG. 5, a circuit diagram of an example of a conventional output circuit, is a schematic diagram for explaining latch-up of the circuit shown in FIG. 1. 1.2.3...Contact, 4...Delay circuit, 11...P-type semiconductor substrate, 12°----
Nfel, 13, 14° 15...N+ diffusion region, 16, 17, 181°, , p+ diffusion region, 19.
20...Gate, c...Capacitance%
Q 1+ Q S # Q s e Q1)...
・P channel tra/raster, Qz eQa sQs
#Qs sQr +QstQto, Q1g...
・N-channel transistor s T 1 mT2...
...parasitic NPN? %T3jT4...
... Parasitic PNP? Njista. ¥-3t

Claims (2)

[Claims] (1) A first transistor of the 10th conductivity type, with the drain connected to the first contact, the gate connected to the input terminal, and the source connected to the first power supply, and the drain connected to the first contact, the gate connected to the input terminal, and the source connected to the a second transistor of a second conductivity type connected to a second power supply; and a third transistor of a second conductivity type whose drain is connected to the first power supply, whose gate is connected to the first contact, and whose source is connected to the second contact. a fourth transistor of a second conductivity type having a drain connected to the second contact, a gate connected to the input terminal, and a source connected to the second power supply;
a fifth transistor of a second conductivity type having a gate connected to the second contact and a source connected to the output terminal, and a second transistor having a drain connected to the output terminal, a gate connected to the input terminal, and a source connected to the second power source. a sixth transistor of conductivity type; a delay circuit having an input end connected to the second contact and an output end connected to the third contact; one terminal connected to the second contact and the other terminal connected to the third contact; and a capacitor connected to the output circuit. (2) The output circuit according to claim (1), wherein the delay circuit is constituted by an even number of stages of inverters.