JPS61283158A - Complementary mos transistor circuit - Google Patents

Abstract

PURPOSE:To prevent a latchup from occurring by forming a well for preventing the latchup between a plurality of separated and insulated wells, and applying the lowest or highest potential therebetween. CONSTITUTION:A P-well region 20 for preventing a latchup separated from P-well regions 2, 13 is connected through a P<+> type region 19 with a negative power source VSS. Thus, when the energizing order of the power sources is GND, VSS, VDD, the GND is first connected and then the power source VSS is connected. Then, an N-type semiconductor substrate 1 is reduced to a negative potential by the junction capacity between the region 2 and an N-type semiconductor substrate 1. Thus, a forward voltage is applied to the region 13 and the substrate 1, and holes generated from the region 13 pass the substrate 1. Since a P-type well region 20 connected with the power source VSS is presented, the holes are implanted to the region 20 to remarkably reduce the holes which arrive at the region 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MOS transistor circuit, and more particularly to a complementary MO8 transistor circuit having a latch-up prevention region.

[Conventional technology]

A complementary MOS transistor circuit (hereinafter referred to as 0M08 circuit) is constructed using, for example, a P-channel MO8 transistor on an N-type semiconductor substrate and an N-channel MOS transistor provided on a P-well region formed in an island shape. There is. Semiconductor devices constructed using such 0M08 circuits are particularly superior in terms of power consumption compared to semiconductor devices using thin circuits, and are used in a wide range of fields. Furthermore, in recent years, analog circuits or analog/digital mixed circuits are increasingly using 0MO8i, and are increasingly being used with multiple power supplies.

Conventional multiple power supply 0M08 circuit, especially in the case of 3 power supplies, the second
The structure is shown in the figure.

In FIG. 2, 13 is, for example, a P well region formed on the N type semiconductor substrate 1, and on this region there is a first well region with 9 as an N source region, 11 as a gate electrode, and 12t-N+ type drain region. N-channel MOS transistors are provided. 8 is a P well region 13 for grounding.
This is the 10-type area.

Further, a first P-channel MO8 transistor is provided on the N-type semiconductor substrate 1, with 14 and 17 serving as P-type drain and source regions, and 16 serving as a gate electrode. Reference numeral 18 denotes an N medium-sized region for applying a power supply VDD to the N-type semiconductor substrate 1. The P medium source region 17 of this tenth P-channel MO8 transistor is connected to the positive power supply VDD, and the gate electrode 16 and P+ drain region 14 are respectively connected to the gate electrode 11 and N+ drain region 12 of the second N-channel MO8 transistor. do. N medium source region 9
Since t- is grounded, this circuit consisting of a first P-channel MO8 transistor and a first ON-channel MO8 transistor takes VIN 1 as an input and VOUTI t-
It becomes a simple inverter with output.

Further, 2 is another P well region which is isolated and insulated from the P well region 13, and a 4t-N+ type north region is formed on the region and connected to the negative power supply vBs, and 6 is a gate electrode;
a second N-channel MOS with 7 as an N-type drain region;
A transistor is provided. 3 is a P-type region, which is connected to the negative power supply VSS and applies VBB to the P well 2. The gate electrode 6 of this second ON channel MO8 transistor becomes an input and is connected to VIN2, and the N medium drain region 7 is connected to the output votr2. In FIG. 2, numerals 5, 10, and 15 are gate oxide films.

[Problem that the invention seeks to solve]

In the above-mentioned conventional three-power CMO8 circuit, a chip, a chip, or a drop may occur depending on the order in which the power is turned on.

In FIG. 2, a P well region 13 and an N type semiconductor substrate 1 are shown.
and P-well region 2f:, respectively, emitter.

Parasitic PNP transistor Trl as base and collector
A parasitic NPN transistor Tr2 is formed with the N0-type source region 4, P-fel region 2, and N-type semiconductor substrate 1 of the N-channel MOS transistor Tr2 as the emitter, base, and collector, respectively. GND
, VBB, and VDD, these parasitic transistors tend to cause chirps, which is a drawback. Third
The diagram shows an equivalent circuit of the parasitic transistor connection in FIG. 2, and will be explained using this diagram.

First, when GNDt- is applied, and then the negative power supply VS8 is applied, the potential of the P well 2 becomes a negative potential V8g, and the junction capacitance between the P well 2 and the N type semiconductor substrate 1 causes the N type semiconductor substrate 1 to become negative. The potential drops. Then, a forward voltage is applied to the P-well 13 and the N-type semiconductor substrate 1, and holes generated from the P-well 13 pass through the N-type semiconductor substrate 1 and enter the P-well 2, and are injected into the negative power supply VSS.

That is, the base potential of the parasitic PNP transistor Tr1 decreases and exceeds the threshold voltage, and Tri begins to turn on and the potential at the resistance dividing point 21 gradually rises. Since the resistance dividing point 21 is connected to the base of the parasitic NPN transistor Tr2 through the raw resistance R6, Tr2 starts to turn on when the threshold voltage is exceeded. Since the parasitic transistors Tri and Tr2 form a positive feedback loop, the current flowing through the parasitic PNP transistor Tri gradually increases, and the disadvantage is that it is eventually thermally destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a complementary MOS transistor circuit with improved reliability and no latch or pull-up.

[Means for solving problems]

A complementary MOS transistor circuit of the present invention includes a MOS transistor having a second conductivity type channel formed on a first conductivity type semiconductor substrate and a second conductivity type well region provided in an island shape and having a different potential from each other. A 0M08 circuit consisting of a MOS transistor having a channel of a first conductivity type, in which a second conductivity search well region for preventing teardown is provided between a plurality of well regions of a second conductivity type, and a second conductivity search well region is provided between the lowest potential source or the highest potential source. The structure is such that it is connected to a potential source.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention. In FIG. 1, 1 is an N-type semiconductor substrate, 13 is an N-type semiconductor substrate 1
A P-well region is formed on top of the P-well region, and 9,
11.12 are N-type source region, gate electrode,
A first N-channel MO8 transistor with an N-type drain region is provided. 8 is a P-type region for grounding the P-well. Further, on the N-type semiconductor substrate 1, a tenth P-channel MOS transistor is provided, each having a p-1-23 drain region, a gate electrode, and a P-type source region at 14°16.17't. Reference numeral 18 denotes an N medium-sized region for applying a power supply VDD to the N-type semiconductor substrate 1.

The P+ type source region 17 of the tenth P channel MO8 transistor is connected to the positive power supply VDD, and the gate electrode 16 and the P medium drain region 14 are connected to the gate electrode 11 and the N medium drain region 12 of the first N channel MO8 transistor.
Since the N medium-sized source region 9 is grounded, this circuit inputs ■rN1 and sVotrrlt-
It becomes a simple inverter with output.

Further, 2 is another P-well region which is isolated and insulated from the P-well region 13, and 4, 6, 7 are placed on that region.
t-N-type source region, gate electrode, and N-type drain region, respectively, and the N0-type source region 4 is connected to the negative power source VSS.
A second N-channel MO8 transistor is provided. 3 is a P type region, which is connected to a negative power supply vssK and is applied to the P well region 2 at Vss t-.

20 is a P-well region for preventing latch-up, which is separated from the P-well region 2.13, and is connected to VSS through the H-type region 19. Therefore, if the power supply order is GND, vss, and VDD, first GNDt- is turned on, and then the negative power supply is turned on vss, P well region 2 and N
Due to the junction capacitance between the N-type semiconductor substrate 1 and the N-type semiconductor substrate 1, the potential of the N-type semiconductor substrate 1 is lowered to a negative potential.

Then, a forward voltage is applied to the P-well region 13 and the N-type semiconductor substrate 1, and the holes generated from the P-well region 13 become N-type semiconductor substrate 1.
type semiconductor substrate 1 . ≠4 However, since the negative potential V88 exists and there is a 9P well region 20, holes are injected into the P well region 20, and the number of holes reaching the P well region 2 is significantly reduced.

In other words, the current amplification factor of the common emitter of the parasitic PNP transistor Tr1 in FIG.
Even if P transistor Trl is turned on, VSS is almost Trl
is applied between the emitter and collector of
The potential of Tr2 does not become high, and Tr2 does not turn on. Therefore, GN
The current between D and Vss, that is, the current flowing between the emitter and collector of Tri, does not increase, and no thermal breakdown occurs.

Although the above embodiments have been described using an N-type semiconductor substrate, a P-type semiconductor substrate may also be used. In this case, the highest potential is fully applied to the N-well region for preventing chipping.

〔Effect of the invention〕

As explained above, according to the present invention, a latch-up prevention fell region is provided between a plurality of isolated and insulated well regions, and a minimum potential or a maximum potential is applied, thereby preventing latch-up from occurring. The effect is great because a reliable complementary MOS transistor circuit can be obtained.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing an embodiment of the present invention, Fig. 2 is a cross-sectional view of a conventional complementary MO8 transistor circuit, and Fig. 3 is an equivalent circuit diagram of a parasitic transistor, parasitic resistance, and parasitic capacitance in Fig. 2. It is. 1... N-type semiconductor substrate, 2, 13, 20...
...P well region, 3,8,19...P raw type region, 4,9...N medium source region, 5,10
, 15... Gate oxide film, 6, 11, 16...
...Gate electrode, 7, 12...N raw drain region, 14...P medium drain region, 17
......P ten-type source region, 18...N+
Type area 几1 * J e R8t R4t R'5
*R1...parasitic resistance, C...parasitic capacitance, Tri...parasitic PNP transistor,
Tr2... Parasitic NPN transistor, VINI
, VIN2 , , , , input, VOUTI e VO
UT 2-...Output, VDD...Positive power supply, V
SS・・・・・・Negative power supply, GND Fig. 1 Fig. 2, -GND Fig. 3

Claims (1)

[Claims] A MOS transistor having a second conductivity type channel formed on a first conductivity type semiconductor substrate, and a first conductivity type channel provided on a plurality of second conductivity type well regions provided in an island shape and having mutually different potentials. In a complementary MOS transistor circuit comprising MOS transistors having a MOS transistor, a second conductivity type well region for latch-up prevention connected to a lowest potential source or a highest potential source is provided between the plurality of second conductivity type well regions. A complementary MOS transistor circuit characterized by: