JPS61153344U - - Google Patents

Info

Publication number
JPS61153344U
JPS61153344U JP3607385U JP3607385U JPS61153344U JP S61153344 U JPS61153344 U JP S61153344U JP 3607385 U JP3607385 U JP 3607385U JP 3607385 U JP3607385 U JP 3607385U JP S61153344 U JPS61153344 U JP S61153344U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
terminal conductor
substrate
small substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3607385U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3607385U priority Critical patent/JPS61153344U/ja
Publication of JPS61153344U publication Critical patent/JPS61153344U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate

Description

【図面の簡単な説明】
第1図はこの考案の集積回路の取付構造を示す
断面図、第2図はチツプサブアツセンブリの断面
図、第3図はチツプサブアツセンブリを取付けた
ガラス基板の斜視図である。 1……絶縁基板、2……導電パターン、3……
封止樹脂、4……ICチツプ、5……ボンデンワ
イヤ、6……電極端子、10……導電接着剤、1
1……ガラス基板、13……回路パターン、30
……液晶表示装置、31……チツプサブアツセン
ブリ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路チツプが載置され、この集積回路チツ
    プの電極端子にワイヤーボンデングされた端子部
    導電体が形成された小基板と、この小基板上の集
    積回路チツプを収納する穴部が形成され、前記端
    子部導電体と電気的に接続される回路パターンが
    形成された大基板とを具備することを特徴とする
    集積回路の取付構造。
JP3607385U 1985-03-15 1985-03-15 Pending JPS61153344U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3607385U JPS61153344U (ja) 1985-03-15 1985-03-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3607385U JPS61153344U (ja) 1985-03-15 1985-03-15

Publications (1)

Publication Number Publication Date
JPS61153344U true JPS61153344U (ja) 1986-09-22

Family

ID=30540931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3607385U Pending JPS61153344U (ja) 1985-03-15 1985-03-15

Country Status (1)

Country Link
JP (1) JPS61153344U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011066373A (ja) * 2009-09-16 2011-03-31 Kinko Denshi Kofun Yugenkoshi 回路板構造
JP2011066372A (ja) * 2009-09-16 2011-03-31 Kinko Denshi Kofun Yugenkoshi 回路板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011066373A (ja) * 2009-09-16 2011-03-31 Kinko Denshi Kofun Yugenkoshi 回路板構造
JP2011066372A (ja) * 2009-09-16 2011-03-31 Kinko Denshi Kofun Yugenkoshi 回路板の製造方法

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