JPS61150362A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a CMOS device having high reliability by a method wherein a first resist mask is formed onto an Si substrate, impurity ions are implanted, an insulating film is shaped through heat treatment, a second resist mask according to the same pattern is formed and the ions of a second impurity are implanted. CONSTITUTION:Si 32 on sapphire 31 is removed through etching in predetermined thickness by an Si3N4 34 mask, P ions are implanted by using a first resist mask 35, B ions are implanted by a second resist mask, oxide films 36 are shaped while employing Si3N4 34 as masks, and Si 32 is separate into Si layers 32a, 32b. Resist masks 37, 39 are formed in succession, and ions are implanted to shape deep N<-> layer 38 and P<-> layer 40 in the layers 32a, 32b. Gate oxide films 41a, 41b are shaped, shallow P<-> layer 42 and N<-> layer 43 are formed through ion implantation by using resist masks, and a CMOS device is completed through a normal method. There is no gate oxide film on deep ion implantation, and the gate oxide films are not deteriorated on shallow ion implantation. Accordingly, the variation of Vth and the lowering of gm can be inhibited, and a latch-up is also prevented, thus acquiring the device having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a MOS transistor in which an ion implantation process is improved.

[Technical background of the invention and its problems]

Conventionally, MOS transistors have been used, for example, in Figures 2(a) to (e).
) is manufactured as shown in

First, a silicon oxide film pattern 2 and a silicon nitride film pattern 3 are formed at a predetermined location 1 on a P-type semiconductor substrate 1, for example. Next, using this nitride film pattern 3 as a mask, boron ions of approximately 10140i14 are implanted into the substrate 1 (as shown in FIG. 2(a)).

Next, field oxidation is performed using the nitride film pattern 3 as a mask to form a field oxide film 4 (see FIG. 2(b)).
). Further, after removing the nitride film pattern 3 and the oxide film pattern 2 thereunder, oxide 1115 is formed on the surface of the substrate 1 surrounded by the field oxide film 4. After that, boron (or arsenic) for controlling the threshold value is applied to the surface of the substrate 1 from above the oxide film 5 at 10!1 to 1012 cIR4.
Ion implantation is performed to form an ion implantation layer 6 (see FIG. 2(C)).
).

Next, a gate electrode 7 made of polycrystalline silicon is formed on the oxide film 5. Subsequently, using this gate electrode 7 as a mask, the oxide 115 is selectively removed to form a gate oxide jl 8. Next, after ion-implanting n-type impurities into the substrate 1 using the gate electrode 7 as a mask,
A heat treatment is performed at around 1000'C to form an N+ type source region 9 and drain region 10 (see Fig. 2 (d)).
. Further, an interlayer insulating film 11 is deposited over the entire surface, and after a densification process, openings are made in the interlayer insulating film 11 corresponding to portions of each of the source and drain regions 9.1o to form contact holes 12. Thereafter, an Afi lead wiring 13 is formed in this cone tact hole 12 to manufacture a MOS transistor (as shown in FIG. 2(e)).

By the way, in MOS transistors manufactured in this way, as the channel length becomes shorter as the degree of integration of devices improves, a gate oxide film of 8 h is injected from 1° of the drain region, causing fluctuations in threshold voltage and gm. bring about a decline. For this reason, in order to solve these problems, it has been considered to reduce the transistor manufacturing process temperature to a lower temperature than in the past. It has been confirmed that lowering the process temperature is very effective and can significantly reduce threshold voltage fluctuations of MOS transistors.

However, in the conventional method, the oxide film 5, which becomes the gate oxide 118, is damaged by the implanted ions in the channel ion implantation step performed in the step of FIG. 2(C).
This has become a major problem as a cause of threshold voltage fluctuations. However, as long as high temperature gas is used,
The damage in the oxide film is sufficiently recovered by the high-temperature process after channel ion implantation, and no problems occur. However, when using a low temperature process, it is necessary to improve the channel ion implantation method.

Furthermore, conventionally, a phenomenon called latch-up occurs due to an increase in the degree of integration of elements. This phenomenon is caused by complementary (C)MOS
The parasitic bipolar transistor of the transistor operates,
This causes the semiconductor device to malfunction. However, in order to solve this problem, in the formation of CMOS transistors, it is necessary to use SO8 (S 1licon On 5apph) which cannot form parasitic bipolar transistors.
ire ) or 5ol(3ilicon Qn In
It is preferable to manufacture a MOS transistor using a 5ulator) substrate. This will be explained with reference to FIG.

21 in the figure is, for example, sapphire. On this sapphire 21, an island-shaped P-type silicon layer 22 is provided. In this silicon layer 22, an N+ type source region 23 and a drain region 24 are formed. A gate electrode fii 27 is provided on the surface channel 25 between these source and train regions 23 and 24 via a gate oxide film 26. In the figure, 28 indicates a field oxide film, and 29 indicates a back channel.

In the MOS transistor thus formed on the SO8 substrate, as shown in FIG. 3, a back channel 29 is formed in the silicon layer 22 on the sapphire 21 side as well as the surface channel 25 under the gate oxide film. Safer the channel part as a way to prevent this back channel? It is necessary to introduce impurities into the silicon layer 22 on the side 21 and create an impurity profile such that the back channel side does not invert. For this reason, in conventional semiconductor devices, in addition to impurity ion implantation (3 ha! low implantation) for threshold control as a channel implant, impurity ion implantation for back channel prevention (Dee) is usually performed.

implants) using the same mask.

Among these channel implanters, Oeep implanters require particularly deep implantation, so the accelerating voltage is high, and therefore damage caused by ion implantation is common. Therefore, when the process temperature is lowered, this causes threshold voltage fluctuation. Therefore, it is desirable to carry out the [)eep implantation prior to forming the gate oxide film, to recover the ion implantation damage through the gate oxidation step, and to lower the subsequent process temperature. On the other hand, since 3-hallow implantation requires accurate control of the transistor threshold, it is better to perform it after the gate oxidation process if the impurity profile can be controlled accurately.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and provides a method for manufacturing a semiconductor device that can suppress fluctuations in threshold voltage and decreases in Q theory due to improvement in the degree of integration of elements, and can also prevent latch-up. The purpose is to

(Summary of the Invention) The present invention provides a first method using a first mask material obtained by exposing the surface of a semiconductor substrate to light through a mask pattern.
a step of ion-implanting an impurity; a step of heat-treating the semiconductor substrate to form an insulating film; and a step of forming an insulating film by using the mask pattern again; This method includes a step of ion-implanting a second impurity into the surface of the substrate, and can suppress fluctuations in threshold voltage and decreases in gm due to increased integration of devices, and can also prevent latch-up. This is something that can be solved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1(a) to (h).

(1) First, for example, after forming an island-shaped silicon layer 32 on the sapphire 31, a silicon oxide film 33 serving as a buffer and a silicon nitride film are formed only on the source, drain, and gate parts (SDG part) on this silicon layer 32. A film 34 was formed. Hereinafter, the sapphire 31 and the silicon layer 32 will be collectively referred to as an SO8 substrate. Subsequently, the silicon nitride film 3
4 as a mask, the silicon layer 32 was etched to a predetermined thickness (FIG. 1 (a> shown). Next, a first resist pattern 3
After forming the resist pattern 35, ions of, for example, phosphorus were implanted into the silicon layer 32 using the resist pattern 35 as a mask (as shown in FIG. 1(b)). Further, after removing the resist pattern 35, ions of, for example, boron were implanted into the silicon 1ii32 using the second resist pattern (not shown) as a mask in the same manner as described above. Thereafter, the second resist pattern was removed, and field oxidation was performed using the silicon nitride film 34 as a mask to form a field oxide film 36. Note that, due to this field oxide film 36, the silicon layer 32 is divided into P-channel and N-channel silicon layers 32.
a132b.

Thereafter, the silicon nitride film 34 and silicon oxide film 33 were removed. (Illustrated in FIG. 1(C)).

(2) First, after forming a resist on the entire surface, the resist is exposed and developed through a first glass mask pattern (not shown) to form a P-channel MOS.
A third resist pattern 37 was formed on the transistor side. Next, using the third resist pattern 37 as a mask, n-type impurities were ion-implanted (deep implant) into the silicon 1132a to form a deep N-type layer 38 (as shown in FIG. 1(d)). Next, after removing the third resist pattern 37 and forming a resist on the entire surface, the resist is exposed and developed through a second glass mask pattern (not shown) to form a resist on the N-channel MOS transistor side. Fourth resist pattern 39
was formed. Thereafter, using this resist pattern 39 as a mask, Q is applied to the other silicon layer 32b in the same manner as described above.
A deep P layer 40 was formed by sep implantation (as shown in FIG. 1(e)).

30 Next, after removing the fourth resist pattern 39,
Thermal oxidation is performed to form gate oxide films 41a and 41b on the silicon layers 32a and 32b on the N-channel side and the P-channel side, respectively.
was formed. Subsequently, using the fifth resist pattern (not shown) cut out from the first glass mask pattern described above as a mask, 3-hallow implantation was performed on the silicon 132a on the N-channel MOS transistor side to form a shallow P layer 42. Next, the fifth resist pattern is removed, and the silicon layer 32 on the P-channel MOS transistor side is removed using a sixth resist pattern (not shown) obtained from the second mask pattern described above as a mask.
A 3-hallow implant was performed on b to form a shallow N-143 (as shown in Figure 1(f)). Furthermore, gate electrodes 44a and 44b made of polycrystalline silicon were formed on the gate oxide films 41a and 4Ib, respectively. Thereafter, using a seventh resist pattern (not shown) as a mask, n-type impurity ions were implanted into the silicon layer 32b to form an N+ type source region 45 and drain region 46. Continuing,
After removing the seventh resist pattern, a p-type impurity layer was ion-implanted into the silicon layer 32a using the eighth resist pattern 47 as a mask to form a P4'' type source region 48 and drain region 49 (see FIG. 1). (j) As shown).Hereafter,
After removing the eighth resist pattern 47, an interlayer insulating layer 1!150 is deposited on the entire surface using a well-known technique, and after a densifying process, interlayer insulating films corresponding to the source, drain regions and gate electrodes are formed. 50 and the like to open a contact hole 51 and form an AN lead-out wiring 52 to manufacture a CMOS transistor (
FIG. 1 (h>illustrated).

However, in the present invention, implantation is performed before forming the gate oxides 1141a and 41b to form shallow P layers 38 and N-1139, respectively.
Hallow implantation is performed after forming the gate oxide film 41a141b to form a deep P layer 42 and a deep N layer 43. Therefore, when performing Qeep implant, gate oxidation is required! 1
! Since gate oxides 111a and 31b are not present, there is no deterioration of these gate oxides 11131a and 31b due to implantation at a high acceleration voltage. In addition, since shallow implantation is usually performed at a low acceleration voltage, gate oxidation JI
Deterioration of 131a and 3b can be significantly reduced. From the above,
Threshold voltage fluctuations and gm decreases can be suppressed, and reliability can be improved. In fact, the CMOS transistor according to the present invention can reduce the threshold voltage fluctuation to 1/10 compared to the conventional one, and can reduce the field oxide film 36 under the gate electrode.
The leakage current due to the field transistor at the edge of the field transistor can be reduced by two to three orders of magnitude.

In the above embodiment, the case where the present invention is applied to the manufacture of CMOS transistors has been described, but the present invention is not limited to this.

〔Effect of the invention〕

As detailed above, according to the present invention, a highly reliable semiconductor device such as a CMOS transistor that can suppress fluctuations in threshold voltage and decrease in gm due to an increase in the degree of integration of elements and prevent latch-up can be manufactured. It is possible to provide a method to do so.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) show a CMO according to an embodiment of the present invention.
Cross-sectional diagram showing the manufacturing method of the S transistor in order of steps, 2nd
Figures (a) to (e) are cross-sectional views showing a conventional MOS transistor manufacturing method in order of steps, and Fig. 3 is a cross-sectional view of a conventional MOS transistor using an SO8 substrate. 31... Insulating substrate (sapphire), 32.32a1
32b...Silicon layer, 33a, 33b...Silicon oxide film, 34...Silicon nitride film, 36...Field oxide film, 37.39.47...Resist pattern, 38.43... N-type layer, 40, 42... P single layer, 44a, 44b... gate electrode, 45.48 ・
... Source region, 46.49 ... Drain region, 50
...Layer separation Rg4.51...Contact hole, 5
2... A℃ extraction wiring. Applicant's agent Patent attorney Takehiko Suzue No. 111 Figure 2

Claims (1)

[Claims] A step of ion-implanting a first impurity using a first mask material obtained by exposing the semiconductor substrate surface through a mask pattern, a step of removing this mask material, and a step of heat-treating the semiconductor substrate to form an insulating film. a step of forming;
a step of obtaining a second mask material by using the mask pattern again, and then ion-implanting a second impurity into the surface of the semiconductor substrate using the second mask material. Method of manufacturing the device.