JPS5978556A - Manufacture of complementary metallic oxide semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process for an SOS-CMOS device which prevents the generation of current leakage by utilizing crystallinity modification due to Si ion implantation. CONSTITUTION:An island form Si layer 102 is provided on an insulation substrate 101. Si is ion-implanted into the region except the neighborhood of the boundary of a p type and an n type MOS transistor, heat treatment is performed, and thus the crystallinity of the ion implanted region is modified. Next, gate oxide films 104 (1041, 1042) and gate electrodes 105 (1051, 1052) of each transistor are formed. An n type impurity is ion-implanted into an n-channel MOS forming region with the gate electrode 1051 and a resist 106 as a mask, and a p type impurity into a p-channel MOS forming region with the gate electrode 1052 and a resist 107 as a mask. At this time, an ion implanted depth becomes shallow at the crystallinity modified region. Thereafter, heat treatment is performed, and accordingly the CMOS device wherein a drain region in the neighborhood of the boundary of each transistor is formed deeply is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary MOS semiconductor device (CMOS) formed in an island-shaped semiconductor layer on an insulating substrate.

[Technical background of the invention and its problems]

CMOS, which is provided on a semiconductor layer on an insulating substrate, has seven transistors (p-channel, n-channel/channel MOS) on an island-shaped semiconductor layer, and their drains/regions are in contact with each other, forming a high-concentration junction between the three. It has a structure that allows A CMOS having an overcast structure has conventionally been manufactured by the following method.

First, an air-insulated island-shaped semiconductor layer 2 is formed on an insulating substrate l made of sapphire or the like, and then gate oxide films 3. , 3. For example, polycrystalline silicon b.
A gate electrode 41142 is then formed. Next, ions of arsenic, which has a small diffusion coefficient, for example, are selectively implanted into the n-channel/I/4AIJ, and boron, for example, is selectively ion-implanted into the p-channel side, and then an activation process is performed.
type source and drain regions 5□, 6 and p-type source and drain regions 52 * 62 are formed respectively to form a CMOS.
(as shown in Figure 1).

In the above-mentioned CMOS, the drain region 61 + of the n-channel and p-channel MOS) run shifter
62 are in contact with each other, and the boundaries between the three are bonded with high concentration, so that the device area can be significantly reduced. however,
Arsenic ion implantation (or thermal diffusion) into the source region 5□, drain region 6, and drain region 6 of the n-channel MOS) run shifter.
If formed using the above method, arsenic may not reach the interface between the island-shaped semiconductor layer 2 and the insulating substrate 1. C of such a structure
In MOS, the level of the inverter input (Vin) is set to L, and the p-channel MOS transistor is turned on.
When the level of the output (Vout) is set to H, the state becomes a forward bias state as shown by the dotted line in FIG.
There was a problem that leakage current occurred due to the bus.

In order to improve the above-mentioned drawbacks, the source and drain regions 5. which constitute a syn shifter (n-channel, p-channel MOS) as shown in FIG. '.

52'+6□/, 621 are the semiconductor layer 2 and the insulating substrate 1, respectively.
In order to prevent the above-mentioned leakage current, the leakage current is formed so as to reach the interface between the two. However, with such a structure, the channel length (Leff) of each transistor' becomes very small, resulting in the inconvenience that a so-called short channel effect appears.

It is also possible to reduce the thickness of the island-shaped semiconductor layer and create a structure in which the source and drain regions of each transistor reach the interface between the semiconductor layer and the insulating substrate without shortening the channel length. Conceivable. however,
As the film thickness of the semiconductor layer on the insulating substrate becomes thinner, the crystallinity deteriorates, and as the device size decreases, the deterioration of the crystallinity significantly adversely affects the device characteristics.

For this reason, recently, the following method has been used to manufacture CMOS in which the short channel effect and leakage current are prevented.

First, a semiconductor layer (for example, a silicon layer) is epitaxially grown on an insulating substrate (for example, a sapphire substrate) 1, and then the silicon layer is selectively removed to form an island-shaped silicon layer 12 whose periphery is insulated from air. do. Next, the n-channel and p-channel MO of the island-shaped silicon layer 12
S) Gate oxide film 13 in each portion where transistors are to be formed.

Gate electrodes 5 & 1 made of polycrystalline silicon via 132
4. ,14. After forming, a resist pattern /15 is formed by photolithography to cover the area where the p-channel MO8) transistor is to be formed, and using the resist pattern 15 and the gate electrode 14 as a mask, an n-type impurity such as arsenic is added to the silicon layer 12. A first arsenic ion implantation layer 16 is formed near the surface of the silicon layer 12 by selectively implanting ions with low implantation energy (as shown in FIG. 3(a)). Subsequently, the resist pattern 15 is removed, and a resist pattern 7 is formed again by photolithography to cover the area where the p-channel MOS transistor is to be formed and the periphery including the game electrode 141. Using the resist pattern 17 as a mask, for example, arsenic is applied. A second ion is implanted into the silicon layer 12 by selectively implanting ions into the silicon layer 12 with high implant energy.
An arsenic ion-implanted layer 18 is formed (as shown in FIG. 3(b)).

Next, the resist butter/17 is removed, and a resist pattern 19 is again formed by photolithography to cover the area where the n-channel MOS transistor is to be formed. Using the resist pattern 19 and the gate electrode 142 as a mask, a p-type impurity 1 such as boron is added. is selectively implanted into the silicon layer 12 with low implantation energy to form a first boron ion implantation layer 2θ near the surface of the silicon h12 (as shown in FIG. 3C). Subsequently, the resist pattern 19 was removed, and the n-channel MO8) was photolithographically etched again.
7 After forming a resist pattern 21 covering the area where the Y transistor is to be formed and the periphery including the gate electrode 14 □, boron ions are selectively implanted into the silicon layer 12 with high implant energy using the resist pattern 2 as a mask to implant silicon. A second boron ion implantation layer 22 is formed inside the layer 12 (as shown in FIG. 3(d)). After that, the resist pattern 21 is removed, heat treatment is performed, and as a result, the 11th and 2nd
The arsenic ion implantation layer 16.18 of the gate electrode 14.1 is activated. N-type source and drain regions 23 are shallow near the gate electrode 14 and reach the interface between the silicon layer 12 and the sapphire substrate 11 in the farther regions.

241 was formed. At the same time, the first and second boron/ion implantation layers 20.22 are activated, and the p-type layer becomes shallow in the vicinity of the gate electrode 14□ and reaches the interface between the silicon layer 12 and the sapphire substrate 1 in the part farther away from the gate electrode 142. An 0MO8 was fabricated with n-channel/p-channel MOS F5 transistors in which the source and drain-in regions (s+242) were in contact with each other and were highly doped.
(Illustrated in FIG. 3(e)).

The 0MO8 obtained by the above-mentioned method is used as the drain region 24 of the run shifter in FIG.
．． , x42 are bonded to each other when they reach the interface between the silicon layer 12 and the +7 layer substrate 1, so that the current leak described above can be prevented, and the gate electrode 14. ．． 1
Source and drain regions around 42 23□, 232, 24
．． ．． Since the 242 portion is shallow, the short channel effect can be prevented. However, the above manufacturing method has a problem in that the process becomes extremely complex because it requires two photo-etching steps and two ion implantation steps compared to the normal 0MO8 manufacturing process. .

[Purpose of the invention]

The present invention can prevent the occurrence of current leakage and short channel effect, and can reduce the photolithography process by one step compared to the conventional method.
The present invention aims to provide a method for manufacturing 0MO8 4AJi that can simplify the process by reducing the number of ion implantation steps by two times.

[Summary of the invention]

The present invention is small (both n-channel and p-channel MO).
8) A step of implanting silicon ions into the semiconductor layer region on the insulating substrate excluding the vicinity of the boundary of the run shifter, and performing heat treatment to modify the crystallinity of the ion implanted region, and implanting a gate into each transistor forming region of the semiconductor layer. A step of selectively forming gate electrodes through an oxide film, and using at least the gate electrodes as a mask, forming an n-channel MO8 of the semiconductor layer.
) An n-type impurity is added to the run shifter formation region, and a p-type impurity is added to the run shifter formation region.
Through the process of ion-implanting pm impurities into the channel MO8 transistor formation region and heat treatment, the ion implantation depth is reduced between the crystalline modified semiconductor layer region and the crystalline modified semiconductor layer region which becomes the drain region of each transistor. Now, taking advantage of the fact that the crystalline unmodified semiconductor layer is deeper, a shallow impurity ion implantation layer is formed in the crystalline modified semiconductor region, and a deep impurity ion implantation layer is formed in the crystalline modified semiconductor layer region. By heat treatment, the drain region near the boundary of each transistor can reach the interface between the insulating substrate and the semiconductor layer, and the other drain region and source region can be formed shallowly. As a result, although the process of forming a resist pattern for ion-implanting Sj into the semiconductor layer increases, the process of forming a resist pattern twice for double-layer ion implantation of n-type and pW as in the conventional method and the process of forming n-type,
The ion implantation process for each p-star can be omitted, and as a result, a highly reliable 0MO8 that prevents current leakage and short channel effects can be easily obtained.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 4(a) to (d).
After epitaxially growing a .mu.m silicon layer, the silicon layer was selectively removed to form an island-shaped silicon N102 whose periphery was insulated with air. Subsequently, a resist pattern 103 is formed by photolithography to expose the nf channel, directly under the gate electrode of the p-channel MOS transistor, and in the vicinity of the gate electrode. Using the resist pattern 103 as a mask, Si is heated at an acceleration voltage of 370 ke.
V, dose ikl X l O”am-2 (Rp=0.
Ion implantation was carried out under the conditions of 58 μm), and additionally 11-2 ion implantation was performed at a voltage of 100 keV and a dose of 2XlOC0IL.
Ion implantation was performed under the condition of (Rp=0.15 μm) (4th
Figure (a) shown). Note that the reason why the ion implantation was performed twice is to simultaneously modify the crystallinity of the sapphire base g1.101-silicon layer 102 interface and the silicon f@xoz surface.

(11) Next, after removing the resist pattern 103, heat treatment was performed at 1000° O in a N2 atmosphere. As a result, the crystallinity of the region of the silicon layer 102 into which Sl ions have been implanted is improved compared to other regions, and the diffusion coefficient for impurities becomes smaller. Next, n-channel MOS)
P-type impurity is added to the planned channel region of the run shifter region.
For example, by implanting boron ions and further p
An n-type impurity, for example, arsenic, was ion-implanted into the intended channel region of the 408F, 7 transistor formation region, and a heat treatment was performed to control the threshold value of each transistor. Subsequently, gate oxide films 104□, 1 are formed in each transistor region.
Gate electrode 10 made of polycrystalline silicon through 04°
58 and 105 □ are selectively formed, respectively, and after forming a resist bag 7106 covering the p-channel MO8) run shifter formation region by photolithography, using the resist pattern 106 and the gate electrode 105 □ as a mask, n-type impurities, For example, arsenic is accelerated at a voltage of 40 keV and at a dose of 2
X 10IIlffi-2~4X101117m
Ion implantation was performed under the following conditions.

At this time, due to the difference in crystallinity of the silicon layer 102, an arsenic ion implantation layer was formed in which the implantation depth was shallow in the crystalline modified region and deep in the crystalline unmodified region (see Fig. 4).
b) As shown).

(11D) Next, the resist pattern 106 is removed and a resist pattern 107 covering the n-channel MOS transistor formation region is formed again by photolithography, and then the resist pattern 107 and the gate electrode ios
Using □ as a mask, apply a pffi impurity, for example, boron, at an acceleration voltage of 40 keV and a dose of lXl0"cIrL72~3
XlO''(m)i ions were implanted. At this time, due to the difference in crystallinity of the silicon layer, the implantation depth was shallow in the crystalline modified region and deep in the crystalline unmodified region. An injection layer was formed (as shown in FIG. 4(C)).

Ov) Next, after removing the resist pattern 107, heat treatment was performed. As a result, the arsenic ion-implanted layers with different implantation depths are diffused, and are shallow in the vicinity of the gate electrode 1051 and reach the interface between the silicon layer 102 and the sapphire substrate 101 in the part far from the gate electrode 1052, and the n-type source and drain regions 10B, , l 091 was formed. At the same time, boron ion implantation layers with different implantation depths are diffused and become shallow near the gate electrode 1052.
1 pole 105. Source and drain regions 1082*109□ reaching the interface between the silicon layer 102 and the sapphire substrate 101 are formed in the portion where the sapphire substrate 101 moves away from the source, and n-type and p-type drain regions 109. , 109. (n-channel/channel, p-channel MOS in which the MOS transistors are in contact with each other and are highly concentrated)
A CMOS with 7 transistors was manufactured and fc (Fig. 4(d)
).

According to the method of the present invention, a CMOS that prevents current leakage and short channel effects can be manufactured using a normal CMOS process except for implanting Si ions using the resist pattern 103 as a mask. Yield improvement can be achieved.

In addition, since the crystallinity of at least the channel region is modified in the above method, the characteristics such as the operating speed of each transistor are similar to those of conventional CMOS whose crystallinity has been modified with Si ions.
Similarly, it can be secured.

Note that in the above embodiment, a portion of the source region of each transistor also reaches the interface between the silicon layer and the sapphire substrate, but the present invention is not limited to this. For example, by performing 81 ion implantation and heat treatment to modify the crystallinity of the silicon layer except for the vicinity of the boundary of each transistor, and then performing the same process as in the example, a shallow source region can be formed as shown in FIG. CM having drain regions 1091° and 1092 that reach the interface between the silicon layer 102 and the sapphire substrate 101 only on the sides that contact each other.
O8 may also be produced.

Although a sapphire substrate was used as the insulating substrate in the above embodiment, the present invention is not limited to this, and other insulating substrates such as a spinel substrate may be used.

In the above embodiment, the island-shaped silicon layer was formed by air insulation, but the island-shaped silicon layer may be formed by dielectric separation.

〔Effect of the invention〕

As detailed above, according to the present invention, current leakage and short channel effects can be prevented, and the process is significantly simplified by reducing the number of photo-etching steps by one and the number of ion-implantation steps by two compared to the conventional method. In addition, it is possible to provide a method for mass-producing CMO8 with high performance and high reliability.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views showing a conventional CMO8 formed on an insulating substrate, and FIGS. 3(a) to (e) are cross-sectional views showing the manufacturing process of a conventional improved CMO8. Figure 4 (
a) to (d) are cross-sectional views showing the manufacturing process of CMO8 formed on an insulating substrate in an example of the present invention, and FIG. 5 is a cross-sectional view showing another example of CMO8 obtained by the method of the present invention. 010゛1...Sapphire substrate, 102.
... Island-shaped silicon layer, 104□, 104. ... Gate oxide film, 1058, 1052 ... Gate electrode, 10
81-. Patent attorney representing applicant Takehiko Suzue

Claims (1)

[Claims] A p-channel MO8) run shifter and an n-channel MOS) run shifter are respectively formed in an island-shaped semiconductor layer provided on an insulating substrate, and the drain regions of each transistor are brought into contact with each other to form a high-concentration junction between the three boundaries. In manufacturing a complementary MOS semiconductor device, a step of implanting silicon ions into the semiconductor layer region excluding at least the vicinity of the boundaries of each of the transistors, and performing heat treatment to break the crystallinity of the silicon ion implanted region; A step of selectively forming a gate electrode in each transistor formation region of the semiconductor layer via a gate oxide film, and applying an n-type impurity to the n-channel MOS transistor formation region of the semiconductor layer using at least the gate electrode as a mask. A complementary type M characterized by comprising the steps of: 8) doping a p-type impurity into the run shifter formation region of the p-channel MO layer.
A method for manufacturing an OS semiconductor device.