JPS61150355A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61150355A JPS61150355A JP59272043A JP27204384A JPS61150355A JP S61150355 A JPS61150355 A JP S61150355A JP 59272043 A JP59272043 A JP 59272043A JP 27204384 A JP27204384 A JP 27204384A JP S61150355 A JPS61150355 A JP S61150355A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- npn
- elements
- chip
- pnp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はＮＰＮ型トランジスタチップとＰＮＰ型トラ
ンジスタチップを含む複数個のトランジスタチップを１
つのパッケージに封止した半導体装置に関するもので、
特に三相モータの速度コントロール等に用いられる。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a plurality of transistor chips including an NPN transistor chip and a PNP transistor chip.
It concerns semiconductor devices sealed in one package.
It is especially used for speed control of three-phase motors, etc.
従来、叙上の目的で形成された半導体装置に第３図に示
される構造のものがある。この半導体装置は外囲器が例
えばエポキシ樹脂でモールド形成された平板状の外囲器
本体部（ｉｏｏ）からリードフレームの端子（１０１，
１０２・・・１１４）を突出し、また。Conventionally, a semiconductor device formed for the above purpose has a structure shown in FIG. In this semiconductor device, the envelope is formed by molding, for example, an epoxy resin, and extends from the flat envelope main body (ioo) to the terminals (101, 101,
102...114) and also.
外囲器本体部に上記端子の一部を導出しているチップベ
ッド（１２１，１２２・・・１２６）にトランジスタチ
ップ（１３１，１３２・・・１３６）が夫々のコレクタ
電極で配設され、他の電極はいずれも夫々がボンディン
グワイヤによって上記各端子に接続されて第４図に示さ
れる回路図に形成される。なお、図によっても明らかな
ように１図の半分のトランジスタチップ（１３１，１３
２，１３３）はＮＰＮトランジスタ、左半分のトランジ
スタチップ（１３４，１３５，１３６）はＰＮＰトラン
ジスタである。また、外囲器本体部（１００）の一方の
主面に第５図に示すように放熱板（１００ａ）がその−
主面を露出して一体にモールド封着されており、この放
熱板は内装されている上記リードフレームに対しモール
ド樹脂を介してリードフレームのトランジスタチップ配
設面の反対側の面に対向する。Transistor chips (131, 132...136) are arranged with respective collector electrodes on chip beds (121, 122...126) from which some of the terminals are led out to the main body of the envelope, and other The electrodes are connected to the respective terminals by bonding wires to form the circuit diagram shown in FIG. As is clear from the figure, half of the transistor chips (131, 13
2, 133) are NPN transistors, and the left half transistor chips (134, 135, 136) are PNP transistors. Further, as shown in FIG. 5, a heat sink (100a) is provided on one main surface of the envelope body (100).
The heat sink is integrally molded and sealed with its main surface exposed, and this heat sink faces the lead frame, which is housed inside, with the mold resin interposed therebetween, to the surface of the lead frame opposite to the transistor chip disposed surface.
叙上の半導体装置は三相のモータに対応させるため、端
子（１０２）と端子（１０９）、端子（１０４）と端子
（１１１）、端子（１０５）と端子（１１２）の各々を
外部配線で接続する必要がある６次に端子が１４本もあ
り。In order to make the above semiconductor device compatible with a three-phase motor, the terminals (102) and (109), terminals (104) and (111), and terminals (105) and (112) are connected by external wiring. There are 14 6th terminals that need to be connected.
外囲器の大きさとしては５０Ｗ程度のモータに適合する
大きさで長さ６０ｍｍ程度になり、上記外部配線の複雑
化と併せて相当のスペースを要するという問題がある。The size of the envelope is about 60 mm in length to fit a motor of about 50 W, and there is a problem in that it requires a considerable amount of space in addition to the above-mentioned complicated external wiring.
この発明は上記半導体装置の問題点に鑑み、外部配線を
含み小型化された半導体装置を提供する。In view of the problems of the semiconductor device described above, the present invention provides a miniaturized semiconductor device including external wiring.
この発明にかかる半導体装置は、そのマウント部が複数
の端子リードの一部に接続したチップベッドに、ＮＰＮ
トランジスタチップとＰＮＰ トランジスタチップを夫
々のコレクタで導電接続してなることを特徴とするもの
である。The semiconductor device according to the present invention has an NPN
The device is characterized in that a transistor chip and a PNP transistor chip are conductively connected through their respective collectors.
以下にこの発明の一実施例につき第１図および第２図を
参照して説明する。なお、説明において、従来と変わら
ない部分については図面に同じ符号をつけて示し説明を
省略し、相違点につき詳述する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In addition, in the description, parts that are the same as the conventional ones are indicated by the same reference numerals in the drawings, and the description thereof will be omitted, and the differences will be described in detail.
第１図に示されるように、３個のチップベッド（３１，
３２，３３）の夫々にＮＰＮトランジスタチップとＰＮ
Ｐ トランジスタチップ（２１，２４ン、（２２，２５
）、（２３，２６）がコレクタで導電接続してマウン１
一部が形成され、これらチップベッドは夫々端子（３，
６゜９）に接続されている。また、上記各トランジスタ
のベースは隣接の端子（２，５，８）（Ｎ Ｐ Ｎ ）
−ランジスタチップ）、（４，７，１０）（Ｐ Ｎ Ｐ
トランジスタチップ）に接続され導出されている。さ
らにＮＰＮトランジスタチップ（２１，２２，２３）の
エミッタは導電パターンによって端子（１１）に、ＰＮ
Ｐトランジスタチップ（２４，２５，２６）のエミッタ
は導電パターンによって端子（７）に接続されて第２図
に示される回路形成が達成されている。As shown in Figure 1, three chip beds (31,
32, 33) respectively with an NPN transistor chip and a PN
P transistor chip (21, 24, (22, 25)
), (23, 26) are conductively connected at the collector to mount 1
These chip beds have terminals (3, 3,
6°9). Also, the base of each transistor above is connected to the adjacent terminal (2, 5, 8) (NP N )
- transistor chip), (4,7,10)(P N P
transistor chip) and is led out. Furthermore, the emitters of the NPN transistor chips (21, 22, 23) are connected to the terminals (11) by the conductive pattern.
The emitters of the P transistor chips (24, 25, 26) are connected to the terminals (7) by conductive patterns to achieve the circuit formation shown in FIG.
この発明によれば、従来１個のトランジスタチップをマ
ウントするのに１つのチップベッドを用いて１個の端子
に導出されていたものを、ＮＰＮ。According to this invention, NPN is used instead of NPN, which conventionally used one chip bed to mount one transistor chip and led out to one terminal.
ＰＮＰ型トランジスタの２個を１つのチップベッドに夫
々のコレクタ電極でマウントし共通の端子に導出するよ
うにした。これにより、端子数が従来の１４から１１に
減少し得て外囲器の大きさを従来の５８ｍｍから３１．
５ｍ■に小型化が達成された。Two PNP transistors were mounted on one chip bed with their respective collector electrodes and led out to a common terminal. As a result, the number of terminals can be reduced from the conventional 14 to 11, and the size of the envelope can be reduced from the conventional 58 mm to 31.
Miniaturization to 5m was achieved.
また、従来外部回路で接続を施していたＮＰＮ。Also, NPN, which was conventionally connected using an external circuit.
ＰＮＰトランジスタのコレクタの接続も省略できたので
、この分を含めて小型化はさらに増長される顕著な効果
がある。Since the connection of the collector of the PNP transistor can also be omitted, there is a remarkable effect that the size reduction is further increased including this part.
第１図はこの発明の一実施例にががる半導体装置のマウ
ント部の断面図、第２図は第１図に示す半導体装置の回
路図、第３図は従来の半導体装置のマウント部の断面図
、第４図は第３図に示す半導体装置の回路図、第５図は
半導体装置の断面図である。FIG. 1 is a sectional view of the mount portion of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1, and FIG. 3 is a sectional view of the mount portion of a conventional semiconductor device. 4 is a circuit diagram of the semiconductor device shown in FIG. 3, and FIG. 5 is a sectional view of the semiconductor device.
Claims (1)
チップベッドにＮＰＮトランジスタチップおよびＰＮＰ
トランジスタチップを夫々のコレクタで導電接続したマ
ウント部と、前記トランジスタのエミッタ、ベースを端
子リードに導電接続した電極導出部とを封止樹脂で封止
してなる樹脂封止型の半導体装置。NPN transistor chips and PNP transistors are connected to multiple terminal leads and a chip bed connected to some of the terminal leads.
A resin-sealed semiconductor device comprising a mount portion in which a transistor chip is conductively connected to each collector, and an electrode lead-out portion in which the emitter and base of the transistor are conductively connected to a terminal lead, which are sealed with a sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272043A JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272043A JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61150355A true JPS61150355A (en) | 1986-07-09 |
| JPH0758748B2 JPH0758748B2 (en) | 1995-06-21 |
Family
ID=17508318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59272043A Expired - Lifetime JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758748B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63206166A (en) * | 1987-02-23 | 1988-08-25 | Toshiba Corp | High-power module |
| US5019893A (en) * | 1990-03-01 | 1991-05-28 | Motorola, Inc. | Single package, multiple, electrically isolated power semiconductor devices |
| JP2011081600A (en) * | 2009-10-07 | 2011-04-21 | Panasonic Corp | Stabilized power supply circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842686A (en) * | 1971-09-30 | 1973-06-21 | ||
| JPS526470A (en) * | 1975-07-07 | 1977-01-18 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS559401A (en) * | 1978-07-05 | 1980-01-23 | Hitachi Ltd | Leed frame |
| JPS59112954A (en) * | 1982-12-08 | 1984-06-29 | バイエル・アクチエンゲゼルシヤフト | Diisocyanate, diisocyanate mixture and manufacture |
-
1984
- 1984-12-25 JP JP59272043A patent/JPH0758748B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842686A (en) * | 1971-09-30 | 1973-06-21 | ||
| JPS526470A (en) * | 1975-07-07 | 1977-01-18 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS559401A (en) * | 1978-07-05 | 1980-01-23 | Hitachi Ltd | Leed frame |
| JPS59112954A (en) * | 1982-12-08 | 1984-06-29 | バイエル・アクチエンゲゼルシヤフト | Diisocyanate, diisocyanate mixture and manufacture |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63206166A (en) * | 1987-02-23 | 1988-08-25 | Toshiba Corp | High-power module |
| US5019893A (en) * | 1990-03-01 | 1991-05-28 | Motorola, Inc. | Single package, multiple, electrically isolated power semiconductor devices |
| JP2011081600A (en) * | 2009-10-07 | 2011-04-21 | Panasonic Corp | Stabilized power supply circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758748B2 (en) | 1995-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3754471B2 (en) | Package / lead frame for optical coupler and manufacturing method thereof | |
| JP2000133767A (en) | Laminated semiconductor package and its manufacture | |
| JPH09312375A (en) | Lead frame, semiconductor device and manufacture thereof | |
| JPH064595Y2 (en) | Hybrid IC | |
| JPH04307943A (en) | Semiconductor device | |
| JP2809945B2 (en) | Semiconductor device | |
| JPS61117858A (en) | Semiconductor device | |
| JPS61150355A (en) | Semiconductor device | |
| JPS6028256A (en) | Semiconductor device | |
| JP2629853B2 (en) | Semiconductor device | |
| JPS62158352A (en) | Resin sealed semiconductor device | |
| US6329707B1 (en) | Twin transistor device with improved collector-base isolation | |
| JP2555522Y2 (en) | Resin-sealed semiconductor device | |
| JP3466354B2 (en) | Semiconductor device | |
| JP2629461B2 (en) | Resin-sealed semiconductor device | |
| KR0129198B1 (en) | Semiconductor package | |
| KR970007842B1 (en) | Plastic semiconductor package | |
| JPH11111910A (en) | Multichip mount semiconductor device and its manufacture | |
| JP2555991B2 (en) | package | |
| JP2912813B2 (en) | Electronic components | |
| JPH01105551A (en) | Electronic device | |
| JPH0645514A (en) | Hybrid integrated circuit | |
| JPH0376260A (en) | Semiconductor integrated circuit | |
| KR900006319B1 (en) | Hybrid ic. | |
| KR910008079Y1 (en) | Leadframe for two chip |