JPH0758748B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0758748B2 JPH0758748B2 JP59272043A JP27204384A JPH0758748B2 JP H0758748 B2 JPH0758748 B2 JP H0758748B2 JP 59272043 A JP59272043 A JP 59272043A JP 27204384 A JP27204384 A JP 27204384A JP H0758748 B2 JPH0758748 B2 JP H0758748B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- transistor
- semiconductor device
- terminal
- npn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明はNPN型トランジスタチップとPNP型トランジス
タチップを含む複数個のトランジスタチップを１つのパ
ッケージに封止した半導体装置に関するもので、特に三
相モータの速度コントロール等に用いられる。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device in which a plurality of transistor chips including an NPN type transistor chip and a PNP type transistor chip are encapsulated in one package, and particularly to a three-phase motor. Used for speed control, etc.
従来、叙上の目的で形成された半導体装置に第３図に示
される構造のものがある。この半導体装置は外囲器が例
えばエポキシ樹脂でモールド形成された平板状の外囲器
本体部（100）からリードフレームの端子（101,102…11
4）を突出し、また、外囲器本体部に上記端子の一部を
導出しているチップベッド（121,122…126）にトランジ
タチップ（131,132…136）が夫々のコレクタ電極で配設
され、他の電極はいずれも夫々がボンディングワイヤに
よって上記各端子に接続されて第４図に示される回路図
に形成される。なお、図によっても明らかなように、図
の半分のトランジスタチップ（131,132,133）はNPNトラ
ンジスタ、左半分のトランジスタチップ（134,135,13
6）はPNPトランジスタである。また、外囲器本体部（10
0）の一方の主面に第５図に示すように放熱板（100a）
がその一主面を露出して一体にモールド封着されてお
り、この放熱板は内装されている上記リードフレームに
対しモールド樹脂を介してリードフレームのトランジス
タチップ配設面の反対側の面に対向する。Conventionally, there is a semiconductor device having a structure shown in FIG. 3 as a semiconductor device formed for the purpose of the above. In this semiconductor device, an enclosure is molded from, for example, an epoxy resin in a flat plate-like enclosure body (100) to lead frame terminals (101, 102 ... 11).
4) is protruded, and the transistor beds (131, 132, ..., 136) are arranged at respective collector electrodes on the chip beds (121, 122, ..., 126) that lead out a part of the terminals to the main body of the envelope, and others. Each of the electrodes is connected to each of the above-mentioned terminals by a bonding wire to form the circuit diagram shown in FIG. As is clear from the figure, the half transistor chips (131, 132, 133) in the figure are NPN transistors, and the left half transistor chips (134, 135, 13).
6) is a PNP transistor. In addition, the enclosure body (10
Heat sink (100a) on one main surface of (0) as shown in FIG.
Is exposed to one main surface and is integrally molded and sealed, and this heat dissipation plate is mounted on the surface of the lead frame opposite to the transistor chip mounting surface of the lead frame through the molding resin with respect to the lead frame. opposite.
叙上の半導体装置は三相のモータに対応させるため、端
子（102）と端子（109）、端子（104）と端子（111）、
端子（106）と端子（113）の各々を外部配線で接続する
必要がある。次に端子が14本もあり、外囲器の大きさと
しては50W程度のモータに適合する大きさで長さ60mm程
度になり、上記外部配線の複雑化と併せて相当のスペー
スを要するという問題がある。The above semiconductor device corresponds to a three-phase motor, so that the terminal (102) and the terminal (109), the terminal (104) and the terminal (111),
It is necessary to connect the terminal (106) and the terminal (113) with external wiring. Next, there are 14 terminals, and the size of the envelope is about 60 mm with a size compatible with a motor of about 50 W, and the problem that it requires a considerable space in addition to the complexity of the external wiring There is.
この発明は上記半導体装置の問題点に鑑み、外部配線を
含み小型化された半導体装置を提供する。In view of the above problems of the semiconductor device, the present invention provides a semiconductor device that includes an external wiring and is downsized.
本発明に係る半導体装置は、夫々にNPNトランジスタチ
ップとPNPトランジスタチップを各々のコレクタで導電
接続してマウントする複数のチップベッドと、該チップ
ベッドに接続するコレクタ端子リードと、前記NPNトラ
ンジスタチップとPNPトランジスタチップのベースを個
々に接続し導出するベース端子リードと、前記複数NPN
トランジスタの各エミッタを共通接続し導出するNPNト
ランジスタのエミッタ端子リードと、前記複数PNPトラ
ンジスタチップの各エミッタを共通接続し導出するPNP
トランジスタのエミッタ端子リードと、前記各チップベ
ッドおよび各端子リードを封止する封止樹脂を具備して
構成されたことを特徴とする。A semiconductor device according to the present invention includes a plurality of chip beds each mounting an NPN transistor chip and a PNP transistor chip by conductively connecting the collectors, collector terminal leads connected to the chip beds, and the NPN transistor chip. A base terminal lead for individually connecting and drawing out the bases of the PNP transistor chip, and the plurality of NPNs.
An emitter terminal lead of an NPN transistor for commonly connecting and deriving each emitter of the transistor and a PNP for commonly connecting and deriving each emitter of the PNP transistor chips.
It is characterized by comprising an emitter terminal lead of a transistor and a sealing resin for sealing the chip beds and the terminal leads.
以下にこの発明の一実施例につき第１図および第２図を
参照して説明する。なお、説明において、従来と変わら
ない部分については図面に同じ符号をつけて示し説明を
省略し、相違点につき詳述する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In the description, parts that are the same as those in the prior art will be denoted by the same reference numerals in the drawings, description thereof will be omitted, and differences will be described in detail.
第１図に示されるように、３個のチップベッド（31,32,
33）の夫々にNPNトランジスタチップとPNPトランジスタ
チップ（21,24）、（22,25）、（23,26）がコレクタで
導電接続してマウント部が形成され、これらチツプベッ
ドは夫々端子（3,6,9）に接続されている。また、上記
各トランジスタのベースは隣接の端子（2,5,8）（NPNト
ランジスタチップ）、（4,7,10）（PNPトランジスタチ
ップ）に接続され導出されている。さらにNPNトランジ
スタチップ（21,22,23）のエミッタは導電パターンによ
って端子（11）に、PNPトランジスタチップ（24,25,2
6）のエミッタは導電パターンによって端子（７）に接
続されて第２図に示される回路形成が達成されている。As shown in FIG. 1, three chip beds (31, 32,
33), NPN transistor chips and PNP transistor chips (21,24), (22,25), (23,26) are conductively connected by collectors to form mount parts, and these chip beds are respectively connected to terminals (3, 6,9) is connected. The bases of the respective transistors are connected to the adjacent terminals (2,5,8) (NPN transistor chips) and (4,7,10) (PNP transistor chips) and led out. Furthermore, the emitter of the NPN transistor chip (21,22,23) is connected to the terminal (11) by the conductive pattern and the emitter of the PNP transistor chip (24,25,2).
The emitter of 6) is connected to the terminal (7) by a conductive pattern to achieve the circuit formation shown in FIG.
この発明によれば、従来１個のトランジスタチップをマ
ウントするのに１つのチップベッドを用いて１個の端子
に導出されていたものを、NPN,PNP型トランジスタの２
個を１つのチップベッドに夫々のコレクタ電極でマウン
トし共通の端子に導出するようにした。これにより、例
えば端子数が従来の14から11に減少し得て外囲器の大き
さを従来の58mmから31.5mmに小型化が達成された。ま
た、従来外部回路で接続を施していたNPN,PNPトランジ
スタのコレクタの接続も省略できたので、この分を含め
て小型化はさらに増長される顕著な効果がある。According to the present invention, what is conventionally led to one terminal by using one chip bed for mounting one transistor chip is used as an NPN / PNP type transistor.
Each chip was mounted on one chip bed with each collector electrode and led out to a common terminal. As a result, the number of terminals can be reduced from 14 in the past to 11 and the size of the envelope can be reduced from 58 mm in the past to 31.5 mm. Further, the connection of the collectors of the NPN and PNP transistors, which has been conventionally connected by an external circuit, can be omitted, so that the miniaturization including this amount has a remarkable effect.
第１図はこの発明の一実施例にかかる半導体装置のマウ
ント部の断面図、第２図は第１図に示す半導体装置の回
路図、第３図は従来の半導体装置のマウント部の断面
図、第４図は第３図に示す半導体装置の回路図、第５図
は半導体装置の断面図である。 1,2…11……端子 21,22,23……NPNトランジスタチップ 24,25,26……PNPトランジスタチップ 31,32,33……チップベッド 100……外囲器本体部 100a……外囲器の放熱板1 is a sectional view of a mount portion of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the semiconductor device shown in FIG. 1, and FIG. 3 is a sectional view of a mount portion of a conventional semiconductor device. 4 is a circuit diagram of the semiconductor device shown in FIG. 3, and FIG. 5 is a sectional view of the semiconductor device. 1,2… 11 …… Terminal 21,22,23 …… NPN transistor chip 24,25,26 …… PNP transistor chip 31,32,33 …… Chip bed 100 …… Enclosure body 100a …… Enclosure Radiator plate
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−9401（ＪＰ，Ａ) 特開 昭48−42686（ＪＰ，Ａ) 特開 昭52−6470（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-55-9401 (JP, A) JP-A-48-42686 (JP, A) JP-A-52-6470 (JP, A)
Claims (1)
ジスタチップを各々のコレクタで導電接続してマウント
する複数のチップベッドと、該チップベッドに接続する
コレクタ端子リードと、前記NPNトランジスタチップとP
NPトランジスタチップのベースを個々に接続し導出する
ベース端子リードと、前記複数NPNトランジスタの各エ
ミッタを共通接続し導出するNPNトランジスタのエミッ
タ端子リードと、前記複数PNPトランジスタチップの各
エミッタを共通接続し導出するPNPトランジスタのエミ
ッタ端子リードと、前記各チップベッドおよび各端子リ
ードを封止する封止樹脂を具備して構成されたことを特
徴とする半導体装置。1. A plurality of chip beds, each of which mounts an NPN transistor chip and a PNP transistor chip by conductively connecting the respective collectors, a collector terminal lead connected to the chip beds, the NPN transistor chip and P.
Connect the bases of the NP transistor chips individually to lead out, the emitter terminals of the NPN transistor to commonly connect and lead out the emitters of the NPN transistors, and connect the emitters of the PNP transistor chips together. A semiconductor device comprising an emitter terminal lead of a PNP transistor to be led out, and a sealing resin for sealing the chip beds and the terminal leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272043A JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59272043A JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61150355A JPS61150355A (en) | 1986-07-09 |
| JPH0758748B2 true JPH0758748B2 (en) | 1995-06-21 |
Family
ID=17508318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59272043A Expired - Lifetime JPH0758748B2 (en) | 1984-12-25 | 1984-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758748B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0740790B2 (en) * | 1987-02-23 | 1995-05-01 | 株式会社東芝 | High power power module |
| US5019893A (en) * | 1990-03-01 | 1991-05-28 | Motorola, Inc. | Single package, multiple, electrically isolated power semiconductor devices |
| JP5413117B2 (en) * | 2009-10-07 | 2014-02-12 | パナソニック株式会社 | Stabilized power circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842686A (en) * | 1971-09-30 | 1973-06-21 | ||
| JPS526470A (en) * | 1975-07-07 | 1977-01-18 | Hitachi Ltd | Semiconductor integrated circuit |
| JPS559401A (en) * | 1978-07-05 | 1980-01-23 | Hitachi Ltd | Leed frame |
| DE3245321A1 (en) * | 1982-12-08 | 1984-06-14 | Bayer Ag, 5090 Leverkusen | DIISOCYANATE OR DIISOCYANATE MIXTURES, A METHOD FOR THE PRODUCTION THEREOF AND THEIR USE FOR THE PRODUCTION OF POLYURETHANE PLASTICS |
-
1984
- 1984-12-25 JP JP59272043A patent/JPH0758748B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61150355A (en) | 1986-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5216279A (en) | Power semiconductor device suitable for automation of production | |
| JPH064595Y2 (en) | Hybrid IC | |
| US5019893A (en) | Single package, multiple, electrically isolated power semiconductor devices | |
| JPH04307943A (en) | Semiconductor device | |
| JP2809945B2 (en) | Semiconductor device | |
| US5309017A (en) | Assembly lead frame with common lead arrangement for semiconductor devices | |
| JPH04216661A (en) | Integrated-circuit package assembly | |
| JPH0758748B2 (en) | Semiconductor device | |
| JP2001085613A (en) | Transfer mold power module | |
| JP3183064B2 (en) | Semiconductor device | |
| JP2629853B2 (en) | Semiconductor device | |
| JP2555522Y2 (en) | Resin-sealed semiconductor device | |
| JPH06132468A (en) | Semiconductor device | |
| JP2002076234A (en) | Resin-sealed semiconductor device | |
| JPH0732216B2 (en) | Semiconductor device | |
| JP2629461B2 (en) | Resin-sealed semiconductor device | |
| JPH0622997Y2 (en) | Insulator-sealed semiconductor device | |
| JPH0364934A (en) | Resin sealed semiconductor device | |
| JP2003037245A (en) | Semiconductor package and application device therefor | |
| JP2900584B2 (en) | Semiconductor device | |
| JPS6234154B2 (en) | ||
| JPS5823469A (en) | Composite power transistor | |
| JPH11111910A (en) | Multichip mount semiconductor device and its manufacture | |
| JPH05211247A (en) | Semiconductor device | |
| KR900006319B1 (en) | Hybrid ic. |