JPS559401A - Leed frame - Google Patents

Leed frame

Info

Publication number
JPS559401A
JPS559401A JP8089578A JP8089578A JPS559401A JP S559401 A JPS559401 A JP S559401A JP 8089578 A JP8089578 A JP 8089578A JP 8089578 A JP8089578 A JP 8089578A JP S559401 A JPS559401 A JP S559401A
Authority
JP
Japan
Prior art keywords
frame
leeds
tabs
leed
equipments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8089578A
Other languages
Japanese (ja)
Inventor
Haruo Kugimiya
Osamu Tachibana
Shigeo Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8089578A priority Critical patent/JPS559401A/en
Publication of JPS559401A publication Critical patent/JPS559401A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To utilize conventional assembling equipments in their entirety by equally spacing adjoining tabs in the longitudinal direction where each pellet is fixed. CONSTITUTION:Leeds 9 to 14 out of a set of multiple leeds which are supported by a leed frame supporter 4, are used as leeds of a package 1. Among these leeds, the reeds 10 and 13 are formed their tips wider and are assigned as tabs 5a and 5b where pellets are fixed. The distance between these tabs 5a and 5b is set equal to 1/2 of a longitudinal frame pitch L of the package 1, and is also equal to the span between tabs 5c and 5d being located on the longitudinal line of the frame. As a result, the leed frame can be fed during assembling in the longitudinal direction with the equal pitch of L/2, thus eliminating special equipments which have different pitches. Consequently, the conventional equipments can be used in their entirety.
JP8089578A 1978-07-05 1978-07-05 Leed frame Pending JPS559401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8089578A JPS559401A (en) 1978-07-05 1978-07-05 Leed frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8089578A JPS559401A (en) 1978-07-05 1978-07-05 Leed frame

Publications (1)

Publication Number Publication Date
JPS559401A true JPS559401A (en) 1980-01-23

Family

ID=13731089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8089578A Pending JPS559401A (en) 1978-07-05 1978-07-05 Leed frame

Country Status (1)

Country Link
JP (1) JPS559401A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158462A (en) * 1980-05-12 1981-12-07 Fujitsu Ltd Lead frame for single inline semiconductor device
JPS61150355A (en) * 1984-12-25 1986-07-09 Toshiba Corp Semiconductor device
WO2004012485A2 (en) * 2002-07-31 2004-02-05 Freescale Semiconductor, Inc. Mounting surfaces for electronic devices
US7012324B2 (en) 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Lead frame with flag support structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158462A (en) * 1980-05-12 1981-12-07 Fujitsu Ltd Lead frame for single inline semiconductor device
JPS6050347B2 (en) * 1980-05-12 1985-11-08 富士通株式会社 Single inline lead frame for semiconductor devices
JPS61150355A (en) * 1984-12-25 1986-07-09 Toshiba Corp Semiconductor device
WO2004012485A2 (en) * 2002-07-31 2004-02-05 Freescale Semiconductor, Inc. Mounting surfaces for electronic devices
WO2004012485A3 (en) * 2002-07-31 2004-04-08 Motorola Inc Mounting surfaces for electronic devices
US6996897B2 (en) 2002-07-31 2006-02-14 Freescale Semiconductor, Inc. Method of making a mount for electronic devices
US7012324B2 (en) 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Lead frame with flag support structure

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