JPS61148873A - Thyristor - Google Patents
ThyristorInfo
- Publication number
- JPS61148873A JPS61148873A JP27112384A JP27112384A JPS61148873A JP S61148873 A JPS61148873 A JP S61148873A JP 27112384 A JP27112384 A JP 27112384A JP 27112384 A JP27112384 A JP 27112384A JP S61148873 A JPS61148873 A JP S61148873A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- intermediate layer
- layer
- type semiconductor
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 239000002344 surface layer Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000009751 slip forming Methods 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42308—Gate electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、サイリスタに関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a thyristor.
従来、高耐圧のサイリスタとして第４図（ト）及び同図
俤）に示す構造のものが使用されている。Conventionally, as a high voltage thyristor, a structure shown in FIG. 4 (G) and FIG. 4 (H) has been used.
図中１は基体であり、基体１上には、Ｐ型半導体層２、
Ｎ型半導体層３．Ｐ型半導体層４が順次積層されている
。Ｐ型半導体層４には、所定の拡散深さの一°表面層５
が形成されている。Ｐ型半導体層４内の一表面層５を囲
む中間層露出部には、ノ９イロ、）？−）を構成するた
めのＮ＋補助領域６が形成されている。−表面層５上に
は、エミッタ電極７が形成され、Ｎ＋補助領域６上には
、補助エミッタ電極８が形成されている。Ｐ型半導体層
４上には、補助エミッタ電極８に近接してｒ−）電極９
が形成されている。In the figure, 1 is a base, and on the base 1, a P-type semiconductor layer 2,
N-type semiconductor layer 3. P-type semiconductor layers 4 are sequentially stacked. The P-type semiconductor layer 4 has a 1° surface layer 5 with a predetermined diffusion depth.
is formed. In the exposed portion of the intermediate layer surrounding the one surface layer 5 in the P-type semiconductor layer 4, there is a layer 4). -), an N+ auxiliary region 6 is formed. - On the surface layer 5, an emitter electrode 7 is formed, and on the N+ auxiliary region 6, an auxiliary emitter electrode 8 is formed. On the P-type semiconductor layer 4, there is an r-) electrode 9 adjacent to the auxiliary emitter electrode 8.
is formed.
ｆ−）電極９の近傍には、グー）ワイヤ１０が設けられ
ている。なお、同図１１は、Ｐ型半導体層２．Ｎ型半導
体層３、及びｐｍ半導体ｒ８４の周面に形成されたベベ
ル面であり、１２は、Ｐ型半導体層４にＮ型半導体層３
の中央部にまで達する深さで形成された第２ペイル面で
ある。A wire 10 is provided near the f-) electrode 9 . Note that FIG. 11 shows the P-type semiconductor layer 2. 12 is a bevel surface formed on the circumferential surface of the N-type semiconductor layer 3 and the pm semiconductor r84;
The second pail surface is formed to a depth that reaches the center of the second pail surface.
このように構成された従来のサイリスタでは、ｒ−ト電
極９に微小電流が使用時に流れて素子の誤点弧を起こす
のを防止するために％ｄマ／ｄｔ耐量を大きくする必要
がある。而して、ｄマ／ｄｔ耐量特性を調べる試験は、
ダート電極９に微小電流を流しながら行っている。この
ｄマ／ｄｔ耐量特性を高めるためＫは、Ｎ＋表面層６の
直下のＰ型半導体層４を広くすれば良いが、その場合に
は素子の順電圧降下特性、オン特性が悪くなる問題があ
る。In the conventional thyristor constructed in this manner, it is necessary to increase the %dma/dt tolerance in order to prevent a minute current from flowing through the r-to-electrode 9 during use and causing erroneous firing of the element. Therefore, the test to check the dma/dt tolerance characteristics is as follows:
This is done while passing a minute current through the dart electrode 9. In order to improve this dma/dt withstand characteristic, K can be made by widening the P-type semiconductor layer 4 directly under the N+ surface layer 6, but in that case, there is a problem that the forward voltage drop characteristics and on-characteristics of the element deteriorate. be.
本発明は、所定の順電圧降下特性を発揮し、しかも高い
ｄマ／ｄｔ耐量を有するサイリスタを提供することをそ
の目的とするものである。An object of the present invention is to provide a thyristor that exhibits a predetermined forward voltage drop characteristic and has a high dma/dt withstand capability.
本発明は、ｒ−トワイヤをノぐイロ、トｒ−ト部以外の
ダートアルミ電極に近づけて設けたこと罠より、所定の
順電圧降下特性を発揮し、しかも、高いｄマ／ｄｔ耐量
を有するサイリスタである。The present invention exhibits a specified forward voltage drop characteristic by placing the r-toe wire close to the dirt aluminum electrode other than the rotor and r-toe parts, and also has high dma/dt withstand capability. It is a thyristor with
以下１本発明の実施例について図面を参照して説明する
。第１図（２）は、本発明の一実施例の断面図、同図ω
）は、同実施例の要部を示す平面図である。図中２０は
、基体２１上に導電型が交互に異なるようＫして４層の
半導体層２２・・・２５を順次積層してなる半導体基板
である。すなわち、半導体基板２０は、基体２１側から
Ｐ型半導体層２２、Ｎ型半導体層ｚｓｓｐｙＪ、半導体
層２４及びＮ＋表面層２５を順次積層した構造を有して
いる。Ｐ型半導体層２４の主面側の所定領域は、中間層
露出部を構成している。この中間層露出部内には、−表
面層２５に近接して？導電型の補助領域２６が所定の拡
散深さで形成されている。また、中間層露出部には、Ｐ
型半導体層２４とＮ型半導体層２３で形成されたＰＮ接
合に交叉してＮ型半導体層２３の内部に達する深さで半
導体基板２ｏの周辺領域に沿うようにして環状溝２１が
形成されている。Ｎ＋表面層２５の主面には第１電極２
８が形成されている。補助領域２６上には、中間層露出
部に接続すると共に、環状溝２７．に沿うようＫして第
２電極２９が形成されている。第２電極２９に対向して
中間層露出部の所定領域上にはｙ −ト３０が形成され
ている。補助領域２６及び第２電極２９とこれらに対向
する環状溝２７．との間の中間層露出部上には、ｆ −
） Ｊ Ｏに対向した領域から連続して？−）ワイヤ３
１が設けられている。？−） Ｊ Ｏ及びｆ−）ワイヤ
３１．とで？−）電極が構成されている。なお、同図３
２は、半導体基板２００局面に形成されたベベル面であ
る。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1(2) is a sectional view of one embodiment of the present invention, and the figure ω
) is a plan view showing main parts of the same embodiment. In the figure, reference numeral 20 denotes a semiconductor substrate formed by sequentially stacking four semiconductor layers 22 . . . 25 of different conductivity types on a base 21. That is, the semiconductor substrate 20 has a structure in which a P-type semiconductor layer 22, an N-type semiconductor layer zsspyJ, a semiconductor layer 24, and an N+ surface layer 25 are sequentially laminated from the base 21 side. A predetermined region on the main surface side of the P-type semiconductor layer 24 constitutes an exposed intermediate layer. In this intermediate layer exposed portion - in close proximity to the surface layer 25? A conductive type auxiliary region 26 is formed with a predetermined diffusion depth. In addition, in the exposed part of the intermediate layer, P
An annular groove 21 is formed along the peripheral region of the semiconductor substrate 2o at a depth that crosses the PN junction formed by the N-type semiconductor layer 24 and the N-type semiconductor layer 23 and reaches the inside of the N-type semiconductor layer 23. There is. The first electrode 2 is provided on the main surface of the N+ surface layer 25.
8 is formed. On the auxiliary region 26, an annular groove 27. is connected to the exposed intermediate layer portion. A second electrode 29 is formed along K. A Y-t 30 is formed on a predetermined region of the exposed portion of the intermediate layer, facing the second electrode 29 . Auxiliary region 26, second electrode 29, and annular groove 27 facing them. On the exposed part of the intermediate layer between
) Continuously from the area opposite J O? -) Wire 3
1 is provided. ? -) J O and f-) Wire 31. Tode? -) the electrodes are configured; In addition, Figure 3
2 is a beveled surface formed on the surface of the semiconductor substrate 200.
このように構成されたサイリスタによれば、第２図に特
性線（Ｉ）Ｋて示すような微弱なｆ−）電流（１ｇ）を
印加してｄマ／ｄｔ耐量試験を行い、同図に特性線（Ｉ
Ｉ）で示す順印加電圧の立ち上がり（傾き）、即ちｄマ
／ｄｔ耐量を調べると、第３図に特性Ｍ （ＩＩ） Ｋ
て示す結果を得た。これに対して従来のサイリスタで同
様の試験を行ったところｄマ／ｄｔ耐量は第３図に特性
線Ｃ■）にて示す結果を示した。これら特性線（ＩＩ）
（Ｆ／）から実施例のサイリスタ４０は、従来のサイ
リスタに比べ１て同じ微弱なｒ−）電流（１ｇ）に対し
て約２倍のｄマ／ｄｔ耐量を有することが判る。このた
め所定。According to the thyristor configured in this way, a dma/dt withstand test was performed by applying a weak f-) current (1 g) as shown by the characteristic lines (I)K in Fig. 2. Characteristic line (I
When examining the rise (slope) of the forward applied voltage shown in I), that is, the dma/dt tolerance, the characteristic M (II) K is shown in Figure 3.
We obtained the results shown below. On the other hand, when a similar test was conducted using a conventional thyristor, the dma/dt withstand capacity showed the results shown by the characteristic line C■) in FIG. These characteristic lines (II)
It can be seen from (F/) that the thyristor 40 of the embodiment has about twice the dma/dt withstand capacity for the same weak r-) current (1 g) compared to the conventional thyristor. For this reason, it is prescribed.
の！電圧、降下特性の下でｄマ／ａｔ耐量を高くして。of! Increased dma/at tolerance under voltage and drop characteristics.
オン特性、を向上させることができる。また、ｒ−トン
。イヤ３１をｙ−トｓｏから第２電極２９偶に延出させ
たこ、とによシ、環状溝２１の傷の。On-state characteristics can be improved. Also, r-ton. By extending the ear 31 from the Y-toe to the second electrode 29, the annular groove 21 is damaged.
発生を防止することができる。Occurrence can be prevented.
以上説明した如く、本発明に係るサイリスタによれば、
所定の順電圧降下特性を発揮し、しかも高いｄマ／ｄｔ
耐量を有し、オ″ン特性を向上させることができる。As explained above, according to the thyristor according to the present invention,
Demonstrates specified forward voltage drop characteristics and high dma/dt
It has high tolerance and can improve on-state characteristics.
第１図（２）は、本発明の一実施例Ｑ断面図、同図ω）
仁：、同実施例の要部を示す平面図、第２図は、順印加
電圧の変化を時間と電圧の関係で示す特性図、第３図は
、ダート電流とｄマ／ｄｔ耐量との関係を示す特性図、
第４図囚は、従来のサイリスタの構成を示す平面図、同
図ω）は、同サイリスタの断面図である。
２０・・・半導体基板、２１・・・基体、２２・・・Ｐ
Ｍ半導体層、２３・・・Ｎ型半導体層、２４・・・Ｐ型
半導体層、２５・・１を表面層、２６・・・補助領域、
２７・・・環状溝、２８・・・第１電極、２９・・・第
２電極、３０・・・ｆ−）、３１・・・？−トワイヤ、
３２・・・ベベル面。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
縛Ｗｊ５ 山FIG. 1 (2) is a sectional view of one embodiment of the present invention Q, the same figure ω)
Jin: A plan view showing the main parts of the same example. Figure 2 is a characteristic diagram showing the change in forward applied voltage as a function of time and voltage. Figure 3 is a diagram showing the relationship between dart current and dma/dt withstand capacity. Characteristic diagram showing the relationship,
FIG. 4 is a plan view showing the configuration of a conventional thyristor, and ω) is a sectional view of the same thyristor. 20... Semiconductor substrate, 21... Substrate, 22... P
M semiconductor layer, 23... N-type semiconductor layer, 24... P-type semiconductor layer, 25... 1 as surface layer, 26... auxiliary region,
27... Annular groove, 28... First electrode, 29... Second electrode, 30... f-), 31...? -Twyer,
32...Bevel surface. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Binding Wj5 Mt.
Claims (1)
の半導体基板に形成する反対導電型の表面層と、この表
面層に隣接する一導電型の中間層露出部と、前記表面層
より離れた位置の前記中間層露出部に形成する反対導電
型の補助領域と、前記半導基板内に前記主面に沿って形
成する２ケ以上の接合と、前記半導体基板の外周附近に
位置する前記中間層露出部に、この中間層に隣接する前
記接合に交叉して設ける環状溝と、前記表面層に接続す
る第１電極と、前記補助領域と前記中間層露出部とに接
続し、前記第１電極を囲み且つ前記環状溝に沿って形成
する第２電極と、前記補助領域及び第２電極に対向する
前記環状溝間に位置する前記中間層露出部に連続形成す
るゲート電極とを具備することを特徴とするサイリスタ
。A semiconductor substrate having four or more layers of alternating conductivity types, a surface layer of an opposite conductivity type formed on this semiconductor substrate, an exposed intermediate layer of one conductivity type adjacent to this surface layer, and a distance from the surface layer. an auxiliary region of an opposite conductivity type formed in the exposed portion of the intermediate layer at a position; two or more junctions formed in the semiconductor substrate along the main surface; and the junction located near the outer periphery of the semiconductor substrate. an annular groove provided in the intermediate layer exposed portion so as to cross the junction adjacent to the intermediate layer; a first electrode connected to the surface layer; and a first electrode connected to the auxiliary region and the intermediate layer exposed portion; a second electrode surrounding one electrode and formed along the annular groove; and a gate electrode continuously formed in the intermediate layer exposed portion located between the annular groove facing the auxiliary region and the second electrode. A thyristor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27112384A JPS61148873A (en) | 1984-12-22 | 1984-12-22 | Thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27112384A JPS61148873A (en) | 1984-12-22 | 1984-12-22 | Thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61148873A true JPS61148873A (en) | 1986-07-07 |
Family
ID=17495647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27112384A Pending JPS61148873A (en) | 1984-12-22 | 1984-12-22 | Thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61148873A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011151063A (en) * | 2010-01-19 | 2011-08-04 | Sansha Electric Mfg Co Ltd | Thyristor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279671A (en) * | 1975-12-25 | 1977-07-04 | Toshiba Corp | Semiconductor device |
| JPS5410234A (en) * | 1977-06-24 | 1979-01-25 | Fuji Photo Film Co Ltd | Desmutting method |
| JPS54143080A (en) * | 1978-04-28 | 1979-11-07 | Toshiba Corp | Semiconductor device |
| JPS5717173A (en) * | 1980-07-04 | 1982-01-28 | Hitachi Ltd | Controlling rectifying device for semiconductor |
-
1984
- 1984-12-22 JP JP27112384A patent/JPS61148873A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279671A (en) * | 1975-12-25 | 1977-07-04 | Toshiba Corp | Semiconductor device |
| JPS5410234A (en) * | 1977-06-24 | 1979-01-25 | Fuji Photo Film Co Ltd | Desmutting method |
| JPS54143080A (en) * | 1978-04-28 | 1979-11-07 | Toshiba Corp | Semiconductor device |
| JPS5717173A (en) * | 1980-07-04 | 1982-01-28 | Hitachi Ltd | Controlling rectifying device for semiconductor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011151063A (en) * | 2010-01-19 | 2011-08-04 | Sansha Electric Mfg Co Ltd | Thyristor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61219172A (en) | Semiconductor component element | |
| JPS609670B2 (en) | thyristor | |
| US3432731A (en) | Planar high voltage four layer structures | |
| JPS61148873A (en) | Thyristor | |
| JPS6130754B2 (en) | ||
| JPS5753944A (en) | Semiconductor integrated circuit | |
| US3990090A (en) | Semiconductor controlled rectifier | |
| JPS5999769A (en) | Semiconductor device | |
| JPS5927108B2 (en) | Semiconductor controlled rectifier | |
| JPH01214055A (en) | Electrostatic breakdown protective device | |
| JPS6257250A (en) | Semiconductor device | |
| JP2730174B2 (en) | Input protection device | |
| JP3253493B2 (en) | Double-sided semiconductor device | |
| JPH088419A (en) | Semiconductor device | |
| JPS5640277A (en) | Semiconductor device | |
| JPS62150774A (en) | High voltage withstanding semiconductor element | |
| JPS62183177A (en) | Semiconductor device | |
| JPS5947755A (en) | Semiconductor device | |
| JPS599955A (en) | Complementary insulated gate field effect semiconductor integrated circuit device | |
| JPS6031112B2 (en) | Schottky diode with PN junction | |
| JPS6074481A (en) | Schottky barrier diode | |
| JPS60154564A (en) | Semiconductor device | |
| JPS6350052A (en) | Semiconductor device | |
| JPS59194466A (en) | Semiconductor device | |
| JPH03215979A (en) | Bidirectional thyristor |