JPS62183177A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62183177A JPS62183177A JP2510986A JP2510986A JPS62183177A JP S62183177 A JPS62183177 A JP S62183177A JP 2510986 A JP2510986 A JP 2510986A JP 2510986 A JP2510986 A JP 2510986A JP S62183177 A JPS62183177 A JP S62183177A
- Authority
- JP
- Japan
- Prior art keywords
- base
- collector
- electrode
- polysilicon film
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 230000005684 electric field Effects 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、プレーナ型トランジスタ構造を含む半導体装
置の高耐圧品種に係り、特にベース領域周縁のベース・
コレクタ間の耐圧を改善した構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high breakdown voltage type of semiconductor device including a planar transistor structure.
This invention relates to a structure with improved breakdown voltage between collectors.
従来、プレーナ型高耐圧トランジスタ構造を含む半導体
装置は、ベース領域周縁部の耐圧を大きくする方法とし
て前記周縁部にフィールドプレート構造（第２図）また
はフィールドリング拡散構造（第３図）を形成し、ベー
ス・コレクタ接合および表面部分の電界強度を弱めるよ
うにしていた。Conventionally, in a semiconductor device including a planar high voltage transistor structure, a field plate structure (FIG. 2) or a field ring diffusion structure (FIG. 3) is formed at the peripheral edge of the base region as a method of increasing the withstand voltage at the peripheral edge of the base region. , the electric field strength at the base-collector junction and surface area was weakened.
上記周縁部の耐圧構造は、ベース・コレクタ接合の主と
して主面近傍の電界を弱めようとするものである。第２
図のフィールドプレート構造は、ベース領域２とコレク
タ領域の周縁部を図示し友ものであるが、ベース電極４
に連結したフィールドプレート８が主面表面の絶縁酸化
ｌｉ！３上で、ベース周縁に延びているようにしている
。ベース・コレクタ間に逆電圧が印加されると、点線で
示した空乏層１ｏが、主面付近においてはベース領域２
の周縁よシ一段と広がる。The voltage-resistant structure of the peripheral portion is intended to weaken the electric field mainly near the main surface of the base-collector junction. Second
The field plate structure shown in the figure shows the peripheral edges of the base region 2 and the collector region, but the base electrode 4
The field plate 8 connected to the insulating oxide li! on the main surface is 3 and extending around the periphery of the base. When a reverse voltage is applied between the base and the collector, the depletion layer 1o shown by the dotted line changes to the base region 2 near the main surface.
The periphery of the area is expanding further.
この構造はベース領域２の拡散層がその周縁部で彎曲が
大きいので、この部分の電界が強くなシ耐圧劣化の原因
となることを防ぐことを意図している。This structure is intended to prevent the diffusion layer of the base region 2 from having a large curvature at its periphery, so that the electric field at this portion is not strong enough to cause deterioration of the withstand voltage.
しかし、図にみるようにＰＮ接合近傍では確かに電界を
弱めているが、フィールドプレート８の端部下方では電
界集中がおきる。However, as shown in the figure, although the electric field is indeed weakened near the PN junction, electric field concentration occurs below the edge of the field plate 8.
またフィールドリング拡散構造は、第３図に示すように
フィールドリング９を基板内に設けたものであるが、同
じように、フィールドリング９の周縁の空乏層１０にお
いて、図の右側にあるペース領域２の側では電界を弱め
るが、左側では電界集中を緩和する効果がない。Furthermore, in the field ring diffusion structure, the field ring 9 is provided in the substrate as shown in FIG. The electric field is weakened on the 2 side, but there is no effect of alleviating electric field concentration on the left side.
本発明の目的は、ブレーナ型トランジスタ構造のベース
領域周縁に設けた電界緩和構造が、その端部においても
有効であるような前記トランジスタ構造を含む半導体装
置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including a Brehner type transistor structure in which an electric field relaxation structure provided at the periphery of the base region is effective also at the ends thereof.
本発明では、ブレーナ型トランジスタ構造の主面に接す
るベース領域周縁において、ベース・コレクタ接合をお
おう絶縁膜上に高比抵抗ポリシリコン族を形成するとと
もに、前記ポリシリコン膜がその端部でペース電極とコ
レクタ領域に接続する外周部電極とに接触するような構
造としたものである。In the present invention, a high resistivity polysilicon layer is formed on the insulating film covering the base-collector junction at the periphery of the base region in contact with the main surface of the Brainer type transistor structure, and the polysilicon film forms a space electrode at the end thereof. The structure is such that it comes into contact with the outer peripheral electrode connected to the collector region.
以下、図面を参照して、本発明の一実施例につき説明す
る。第１図はＮＰＮ型ブレーナトランジスタの断面図を
示したもので、ペース領域２の周縁部は絶縁酸化膜３で
おおわれている。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of an NPN type brainer transistor, in which the periphery of the space region 2 is covered with an insulating oxide film 3.
絶縁酸化膜３上には高抵抗を有するポリシリコン膜７を
設け、この２重膜はコレクタ領域１の表面に、外周部電
極６（Ｎ＋部分を介してコレクタ領域１と接続している
）まで延長され、ペース電極４と外周部電極６とを高抵
抗で電気的に接続しである。A polysilicon film 7 having high resistance is provided on the insulating oxide film 3, and this double film extends to the surface of the collector region 1 up to the outer peripheral electrode 6 (connected to the collector region 1 via the N+ part). It is extended and electrically connects the pace electrode 4 and the outer peripheral electrode 6 with high resistance.
ベース・コレクタ間に逆バイアスを印加すると、ＰＮ接
合降伏電圧に達するまでは、高抵抗ポリシリコン膜７を
通じて、微弱電流が流れ、電圧降下がほぼ直線的に生じ
、その結果ベース・コレクタ間の逆バイアスをベースか
ら外周部に向って距離に比例して分圧していく。ポリシ
リコン族７の各部の電位は絶縁酸化ａ３を介して半導体
主面に影響を与え、空乏層１０の広がシを延長させる方
向に働き、図示のよう電界集中を防ぐことができる。When a reverse bias is applied between the base and collector, a weak current flows through the high-resistance polysilicon film 7 until the PN junction breakdown voltage is reached, causing a voltage drop almost linearly, resulting in a reverse bias between the base and collector. The bias is divided in proportion to the distance from the base to the outer periphery. The potential at each part of the polysilicon group 7 affects the main surface of the semiconductor through the insulating oxide a3, acts in a direction to extend the depletion layer 10, and prevents electric field concentration as shown in the figure.
以上、詳細に説明したように、高抵抗ポリシリコン膜を
ペース領域周縁部の絶縁酸化膜上に設けることにより、
ベース・コレクタ間に逆バイアスを印加したときに前記
ポリシリコン族に微弱電流が流れ、前記絶縁酸化膜下の
半導体表面の電界集中を防ぐことができた。これによっ
てベース・コレクタ間耐圧の高い半導体装置を得ること
ができる。As explained above in detail, by providing a high-resistance polysilicon film on the insulating oxide film at the periphery of the space region,
When a reverse bias was applied between the base and the collector, a weak current flowed through the polysilicon group, making it possible to prevent electric field concentration on the semiconductor surface under the insulating oxide film. This makes it possible to obtain a semiconductor device with a high base-collector breakdown voltage.
第１図は本発明の一実施例の、第２図、第３図は従来例
のそれぞれの断面図である。
１・・・コレクタ領域、 ２・・・ペース領域、３・
・・絶縁酸化膜、 ４・・・ペース電極、５・・・
コレクタ電極、 ６・・・外周部電極、７・・・ポリ
シリコン族、８・・・フィールドプレート９・・・フィ
ールドリング。FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional example. 1... Collector area, 2... Pace area, 3...
...Insulating oxide film, 4...Pace electrode, 5...
Collector electrode, 6... Outer peripheral electrode, 7... Polysilicon group, 8... Field plate 9... Field ring.
Claims (1)
周縁において、ベース・コレクタ接合をおおう絶縁膜上
に高比抵抗ポリシリコン膜を形成するとともに、前記ポ
リシリコン膜がその端部でベース電極とコレクタ領域に
接続する外周部電極とに接触するような構造を含むこと
を特徴とする半導体装置。A high resistivity polysilicon film is formed on the insulating film covering the base-collector junction at the periphery of the base region in contact with the main surface of the planar transistor structure, and the polysilicon film is connected to the base electrode and the collector region at the end thereof. A semiconductor device characterized by including a structure that makes contact with a peripheral electrode to be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2510986A JPS62183177A (en) | 1986-02-06 | 1986-02-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2510986A JPS62183177A (en) | 1986-02-06 | 1986-02-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183177A true JPS62183177A (en) | 1987-08-11 |
Family
ID=12156758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2510986A Pending JPS62183177A (en) | 1986-02-06 | 1986-02-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183177A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01231367A (en) * | 1988-03-11 | 1989-09-14 | Sanken Electric Co Ltd | Manufacture of semiconductor device |
| JPH02170469A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Semiconductor device |
-
1986
- 1986-02-06 JP JP2510986A patent/JPS62183177A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01231367A (en) * | 1988-03-11 | 1989-09-14 | Sanken Electric Co Ltd | Manufacture of semiconductor device |
| JPH0817228B2 (en) * | 1988-03-11 | 1996-02-21 | サンケン電気株式会社 | Method for manufacturing semiconductor device |
| JPH02170469A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Semiconductor device |
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