JPS6114676B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides MOS (Metal-Oxide-
The present invention relates to a semiconductor device having a semiconductor device structure, and more particularly to a meandering channel MOS transistor structure that can increase the effective drain-source voltage applied to a transistor with a long channel width.

In drive circuits for driving relatively large capacitive loads such as MOS-structured ROM, RAM, or CCD, a push-pull circuit configuration with low power consumption is used as the final stage circuit that can directly drive the load. Commonly used. Such a push-pull circuit shares the source of a transistor whose drain is supplied with power and the drain of a transistor whose source is grounded, and charges and discharges a load by receiving complementary pulses whose phases are inverted from each other to the gates of each transistor. It consists of two MOS transistors that can supply the output current for These two MOS transistors usually have a channel width W that is extremely long (for example, about 0.5 mm to 2 mm) compared to the channel length in order to obtain a large channel conductance capable of driving a large capacitance load. In order to reduce the area and improve yield, it was realized with a meandering channel type MOS structure. However, in order to increase the integration density, it is common for the finger diffusion layers of the drain and source, which have a comb-shaped structure forming a meandering channel, to be equal or narrow in width. Ta. The finger diffused resistance of the drain or source due to this meandering channel structure is considered to be too large to be ignored in a transistor with a very long channel width (very large channel conductance). That is, since the current flowing through a transistor with a very long channel width is large, the effective drain-source voltage V actually applied to the channel section due to the voltage drop in the finger diffusion resistance section is
There was a problem with _{the DS} becoming smaller. For this reason,
The mutual conductance gm of the linear region when a channel is formed becomes equivalently small. The structure of a conventional meandering channel transistor will be explained in detail with reference to the drawings.

FIG. 1 shows the structure of a conventional meandering channel type MOS transistor. In the same figure, drain 1
2. A gate electrode 13 made of either Al or polycrystalline Si is provided on the semiconductor substrate 14 via a gate oxide film (not shown), spanning the diffusion layer forming the source 11. Channel area 1
form 5. The finger diffusion layer 12' forming the drain for the two channel regions is A.
Diffusion resistance Yd determined from the resistivity of the diffusion layer between −A′
has. Similarly, the finger diffusion layer 11' forming sources for the two channel regions also has a diffusion resistance Ys between B and B'. Since the widths 1 ₁ and 1 ₂ of the finger diffusion layers 12' and 11' of the drain and source are equal or approximately the same, the diffusion resistance of the source and drain is
Become Ydrs. Since the width of the channel constituting the transistor is large, the drain current flowing between the drain and the source when the channel is formed is large. As a result, when a power supply voltage of V _DD is supplied to the drain 12, the drain-source voltage V _DS applied to the effective channel section near the midpoint of A-A' is equal to Yd from the power supply voltage V _DD . /2+Ys/2Yd
It is the value obtained by subtracting the voltage due to the voltage drop in the diffused resistance. Drain finger diffusion layer 12'
The effective voltage V _DS applied between the end A' of the source 11 and the end B' of the source finger diffusion layer 11' and the drain 12 is also the same. This voltage drop is so large that it cannot be ignored compared to the power supply voltage V _D . Therefore, the effective mutual conductance gm (linear region) of the active region where the channel is formed is equivalently reduced. Such a phenomenon has the effect of effectively increasing the output impedance of the push-pull circuit and slowing down the dynamic switching speed when driving a load.

The present invention has been made to alleviate such drawbacks, and its purpose is to reduce the effective drain density when forming a channel of a MOS transistor.
It is an object of the present invention to provide a semiconductor device having a MOS structure that allows a large source voltage.

According to the present invention, a semiconductor substrate is formed on a semiconductor substrate.
A semiconductor device with a MOS structure, which has a meandering channel shape with a channel width that is extremely long compared to the channel length.
In a MOS transistor, the width of one of the finger diffusion layers as a source or drain with a comb-shaped structure forming two channel portions on both sides is equal to the width of one of the finger diffusion layers of the other finger diffusion layer. It is possible to obtain a semiconductor device characterized by a structure in which the diffusion resistance from the root to the tip of the finger diffusion layer has a negligibly large value compared to the width of the finger diffusion layer.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the semiconductor device of the present invention. In the figure, a source 11 and a drain 12 for configuring a basic MOS transistor are
It is formed on the semiconductor substrate 14 as a region in which a highly concentrated impurity having a conductivity type opposite to that of the substrate is diffused. Here,
Although the semiconductor substrate can be implemented using either a P-type conductive material or an N-type conductive material, in this specification, for convenience, an example using a P-type conductive substrate will be described. The source and drain diffusion layers 11 and 12 are
Both can be performed using the same process, and are highly concentrated N ⁺ impurity layers formed by diffusing phosphorus impurities into a P-type substrate. Further, the gate electrode for forming the channel region 15 on the surface of the semiconductor substrate 14 is formed on the substrate via an oxide film, for example, SiO ₂ .
This is a layer 13 of Al or polycrystalline Si. This gate electrode 13 is a highly conductive film with low resistivity, and as shown in FIG.
1 and 12 partially overlap with each other via an oxide film (not shown), forming a meandering channel. A transistor with such a MOS structure can be easily manufactured using standard semiconductor process technology.
The diffusion layer usually has a layer resistance of several Ω/□ to several +Ω/□, which is a value so large that it cannot be ignored compared to the low resistivity gate electrode. Among the diffusion layers, a low resistivity electrode layer 13' made of Al or polycrystalline Si, which receives power supply from the drain terminal D, is in contact with the drain diffusion layer 12 through a contact hole 16 partially opened in the oxide film. are doing. In addition, the source diffusion layer 11 also has Al extending from the source terminal S.
Alternatively, a low resistivity electrode layer 13' of polycrystalline Si is in contact through a contact hole 16. These electrode layers 13', 13' are manufactured by the same process as the gate electrode 13. Therefore, the potentials at points A and B shown in FIG. 2 can be considered to be equal to the potentials at the drain end D and source end S, respectively.
However, in the meandering channel MOS structure, the source
Since the drain is formed in a comb-like shape, the potential at the source finger tip B' during channel formation is slightly lower than the potential at the source tip S due to a voltage drop caused by the diffusion resistance Ys of the source finger diffusion layer 11'. It gets expensive. On the other hand, the drain finger diffusion layer 12'
The electric potential at the tip A' of the finger part is determined by the width ' ₁ of one of the drain finger diffusion layers 12' for the two channel regions, which is a feature of the present invention, and the width '1 of the source finger diffusion layer 11'. one width 1
₂ , the diffusion resistance Yd is set to a value close to the potential of the drain end D by making the diffusion resistance Yd negligible. Therefore, the effective drain-source voltage V _DS applied to the channel region 15 of the MOS transistor is calculated by subtracting only the voltage drop due to the diffusion resistance in the source finger diffusion layer 11' from the voltage between the drain D and source S. value. The structure of this embodiment is used as a MOS transistor with the drain D connected to the power supply of a push-pull circuit, and its effect is greatly exhibited.Normally, the stray capacitance of the drain diffusion layer 12 receiving the power supply is determined by how large it is. does not affect the dynamic characteristics. By utilizing such characteristics, it is possible to design the width 1 ₁ ' of the drain finger diffusion layer 12' to be sufficiently large. Conversely, since the MOS transistor connected to the power supply side transistor of the push-pull circuit is used, it is desirable to design the stray capacitance of the source width as small as possible in order to improve the dynamic switching speed. Furthermore, transistors with large channel widths, such as push-pull circuits, tend to occupy a large area within the chip of the entire drive circuit.
Therefore, by designing the width of one or both of the drain and source finger diffusion layers to be as small as possible, the area occupied by the MOS transistor as a unit element can be reduced. As a result, the manufacturing yield of individual ICs can be increased,
This leads to lower costs. From the above, the width ₁₂ of one of the source finger diffusion layers 11' is designed to be small even if some diffusion resistance is sacrificed. It can be seen that if the width _1'1 of one of the drain finger diffusion layers 12 is set large as in the embodiment shown above, the effective V _DS applied to the channel section can be made larger than in the conventional structure. That is, the effective linear region mutual conductance gm (=WCo μeffV _DS /L) of the active region of the channel, which depends on V _DS , can be equivalently larger than the conventional value. Here, L, W, Co, and μeff represent the effective channel length, effective channel width, oxide film capacitance, and effective electron mobility of the MOS transistor, respectively. big gm
When this is obtained, the output impedance seen from the source becomes small when used in a push-pull circuit, so that the current that can flow from the source end S to the load becomes large. As a result, the switching speed when charging a capacitive load can be increased.

FIG. 3 shows another embodiment of the semiconductor device of the present invention. In this figure, the same numbers or symbols as in FIG. 2 represent the same components. In the same figure, the source finger diffusion layer 1 is opposite to the case of FIG.
1' width 1' ₂ is the drain finger diffusion layer 1
2' shows the structure of a MOS transistor configured to be larger than the width 1'. In the case of such a structure, the voltage drop between B and B' of the source finger diffusion layer 11' is negligibly small, and the potential of B' becomes approximately equal to the potential of the source end S. The detailed contents are the same as those in FIG. 2 and can be easily understood, so the explanation thereof will be omitted. In the MOS transistor having the structure shown in FIG. 3, the voltage drop between the drain end D and the source end S is only the voltage due to the diffusion resistance of the drain finger diffusion layer 12'.
The effective V _DS applied to the channel section can be larger than that of the conventional structure. This structure is used as a source-grounded MOS transistor in a push-pull circuit and exhibits its effectiveness to a great extent, since no matter how large the stray capacitance of the grounded source diffusion layers 11 and 11' is, it does not affect the dynamic characteristics. , the width _1'2 of one finger diffusion layer 11' can be made sufficiently large. As a result, a larger value than before can be obtained as the effective linear region mutual conductance gm during channel formation. That is, the current when discharging the load through the drain end D is large, and the switching speed when discharging the capacitive load can be increased.

As is clear from the above explanation, according to the present invention, the effective mutual conductance at the time of channel formation
A serpentine channel MOS transistor with a large gm can be obtained. In particular, the semiconductor device of the present invention has a structure useful for realizing an IC or LSI with a high-density MOS structure, and is useful for configuring a driver for driving capacitive loads such as MOS ROM, RAM, and CCD. suitable for Furthermore, the present invention can be applied to ordinary MOS
Since the structure is a semiconductor device itself, it is easy to manufacture it by sharing part of the CCD process. In addition to CCD, the above-mentioned MOS
It is also possible to integrate on chips such as ROM and RAM.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the structure of a conventional meandering channel type MOS transistor, FIG. 2 is a diagram showing an embodiment of the semiconductor device of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. be. 11, 11', 12, 12'...N ⁺ diffusion layer, 1
3, 13', 13''...Al or polycrystalline Si, 14...
Semiconductor substrate, 15...channel region, 16...contact hole.

Claims (1)

[Claims] 1 A semiconductor device with a MOS structure formed on a semiconductor substrate, and a source or drain with a comb-shaped structure in which two channel parts are formed on both sides in a meandering channel MOS transistor with a channel width that is extremely long compared to the channel length. Among the finger diffusion layers as shown in FIG. A semiconductor device characterized by a structure in which resistance has a negligibly large value.