JPH0715792B2 - Bootstrap circuit - Google Patents

Description

The present invention relates to a boot strap circuit.

In a dynamic RAM (random access memory) composed of a MOSFET (insulated gate field effect transistor), in order to increase the write / read level for the memory cell, in other words, the switching MOSFET of the memory cell is used. A word boost circuit is known in which the selection level of the word line is increased in order to prevent the writing / reading level from being lost by the threshold voltage. However, the conventional boot strap circuit has a problem that the boot efficiency is not sufficient and a desired word line selection level cannot be obtained.

As a result of research on this phenomenon, it was found that the cause was as follows.

The bootstrap capacitor C _B is composed of a MOS capacitor, and causes a minority carrier during operation. Therefore, as shown in the layout diagram of FIG. 1, in order to prevent the store data of the memory array M-ARY section from being destroyed by the minority carrier, the boot strap capacity C _B is set to the minority carrier. Is formed so as to be separated from the memory cell portion by a diffusion distance (usually 400 to 600 μm) or more.

On the other hand, the pulse generation circuit φ _X -G and the delay circuit D which constitute the boot strap circuit are designed to shorten the output line thereof.
It is provided close to the memory array section. And
Peripheral circuits such as various signal generation circuits, a main amplifier, a data input buffer and a data output buffer are formed between the pulse generation circuit φ _X -G, the delay circuit D and the boot strap capacitance C _B. is there. Since the wirings forming these peripheral circuits and the wirings for the boot strap capacitance C _B intersect, a relatively large cross-under resistance occurs, and the wiring length for the boot strap capacitance C _B becomes relatively long. As a result, as shown in the equivalent circuit diagram of FIG. 2, parasitic resistances R ₁ and R ₂ are generated.

Further, between the boot strap capacitor C _B MOS capacitance of the diffusion layer side electrode and the substrate constituting the (-V _BB) are those relatively large parasitic capacitance Clb is formed.

Therefore, as shown in the timing chart of FIG. 3, when the output pulse φ _X from the pulse generation circuit φ _X -G rises to the high level (V _CC ), this voltage V _CC is in the serial form. Since it is applied to the bootstrap capacitance C _B and the parasitic capacitance C lb, the potential of the node N on the diffusion layer side of the bootstrap capacitance C _B becomes an intermediate voltage due to charge division. Will be lifted to. At this time, since the output level of the delay circuit D is the ground potential of the circuit, it acts so as to pull out the charge of the parasitic capacitance Clb. However, the parasitic resistance R ₂ having a relatively large resistance value makes it difficult to reach the ground potential. Dont return. For this reason, as shown in FIG. 3, the swing level of the bootstrap capacitance C _B other end node N becomes as small as V _CC −V _1, and the φ _X bootstrap voltage is also reduced. It becomes something that becomes small.

An object of the present invention is to provide a boot strap circuit having an improved boost efficiency.

Other objects of the present invention will be apparent from the following description and drawings.

Hereinafter, the present invention will be described in detail together with examples.

FIG. 4 shows an equivalent circuit diagram of an embodiment of the present invention.

In this embodiment, in order to quickly extract the charge of the parasitic capacitance Clb in the boot strap circuit composed of the boot strap capacitance C _B as shown in FIG. 1, the pulse generation circuit φ _X -G and the delay circuit D thereof. , MOSFET Q
Then, an inverter IV for forming an inverted signal ▲ ▼ of the delayed signal φ _X ′ is newly added.

The MOSFET Q is formed in proximity to the boot strap capacitor C _B, is provided between the ground potential of the diffusion layer side of the electrode and the circuit of the boot strap capacitor C _B. On the other hand, the above inverter
IV is not particularly limited, but is provided in the vicinity of the delay circuit D side, and the delay signal φ _X ′ (or φ
_X signal may be used) to generate an inverted signal thereof and control the MOSFET Q.

The resistors R ₁ and R ₂ are wiring resistors similar to the above,
Reference numeral ₃ is a similar wiring resistance due to the wiring connecting between the inverter IV and the gate of the MOSFET Q.

The operation of this embodiment circuit will be described with reference to the timing chart of FIG.

When the output pulse φ _{X of the} pulse generation circuit φ _X -G rises to the high level (V _CC ), the charge strapping is performed on the boot strap capacitance C _B and the parasitic capacitance Clb. Therefore, according to the capacitance ratio, the boot strap capacitance is changed. Capacitance C _B and parasitic capacitance Cl
The node N of the electrode on the diffusion layer side of the boot strap capacitance C _B , which is the connection point with b, is raised to the intermediate voltage V ₁ as described above. However, in this embodiment, the MOSFET Q is turned on by the high level of the inverted delay signal ▲ ▼ formed by the inverter IV, and the MOSFET Q is MO
Since it is provided close to the S capacitance C _B , the wiring resistance R
Regardless of ₂ , the charge of the parasitic capacitance Clb is pulled out at high speed to bring the potential of the node N to the ground potential of the circuit. Therefore, the voltage between both electrodes of the boot strap capacitor C _B can be made equal to the level of the output pulse φ _X.

Then, the delay signal φ _X ′ of the delay circuit D becomes high level (V
Becomes a _CC), the voltage V _CC held in the boot strap capacitor C _B to the voltage V _CC is added, The bootstrap voltage can be obtained.

When the word line selection level of dynamic RAM is formed with such a high voltage, switching of the memory cell is performed.
Write / read levels can be transferred to / from memory cells without level loss due to the threshold voltage of the MOSFET.

Further, since the dynamic conductance of the switching MOSFET can be increased, writing / reading levels can be exchanged at high speed.

As a result, it is possible to improve the power supply margin, the noise margin, and the α-ray intensity in the dynamic RAM.

FIG. 6A is a schematic plan view of the boot strap capacitance C _B and MOSFET Q of one embodiment of the present invention, and FIG. 6B is a schematic sectional view thereof.

In the figure, each semiconductor structure is formed by a known semiconductor manufacturing method.

A semiconductor substrate is indicated by reference numeral 1.

A field ₂ indicates a field SiO ₂ film.
The thin SiO ₂ film indicated by symbol 3 has MOS capacitance C _B and MOS
This is the gate insulating film of FET Q. Although not particularly limited, the gate electrode 6 made of conductive polysilicon constitutes one electrode of the boot strap capacitance C _B , and the pulse φ
_X is applied.

The diffusion layer 4 formed on the substrate 1 along the outer periphery of the gate electrode 6 has the other electrode of the boot strap capacitance C _B ,
Configure the drain electrode of MOSFET Q. The boot strap capacitance C _B acts as a MOS capacitance as a result of the formation of the inversion layer as shown by the dotted line in the figure when the above-mentioned pulse φ _X is applied to the gate 6.

In addition, along the outer periphery of the diffusion layer 4 via the insulating film 3.
A gate electrode 7 forming the MOSFET Q is formed. The gate electrode 7 is not particularly limited, and is made of conductive polysilicon, and the inverted delay signal {circle over ()} is applied.

Then, along the outer periphery of the gate electrode 7, on the substrate 1.
A diffusion layer 5 forming the source of MOSFET Q is formed. The diffusion layer 5 is provided with the ground potential of the circuit.

In addition, the diffusion layer 4 is formed on the left and right central portions of the gate electrode 6
The reason for expanding to the side is to form a contact region for the diffusion layer 4.

In the semiconductor structure of this embodiment, the electrode on the diffusion layer side of the MOS capacitor and the drain of the MOSFET Q can be integrally formed,
Since no wiring is required between them, a high degree of integration can be realized, and the charge of the parasitic capacitance Clb between the inversion layer and the substrate can be extracted extremely quickly. Also,
Since the MOS capacitor electrode 6 and the MOSFET Q gate can be formed at the same time, the number of manufacturing steps does not increase.

Further, the diffusion layer (source) 5 to which the ground potential of the MOSFET Q is applied can also act as a guard ring for the minority carrier in the MOS capacitor.

The present invention is not limited to the above embodiment.

As long as the bootstrap capacitance and the MOSFET Q for removing the charge of its parasitic capacitance are formed close to each other without surrounding the boost capacitance Cb as shown in FIG. Good.

In addition, the inverter IV that forms the inverted signal ▲ ▼
It may be formed near the MOSFET Q.
Further, although the description has been given assuming that the boost capacitor is formed by the MOSFET in the text, it may be a two-layer wiring structure with an oxide film interposed therebetween.

The present invention can be widely used as a boot strap circuit built in a MOS semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an example of a conventional dynamic RAM, FIG. 2 is an equivalent circuit diagram of the boot strap circuit, FIG. 3 is a timing diagram for explaining its operation, and FIG. , An equivalent circuit diagram showing an embodiment of the present invention, FIG. 5 is a timing diagram for explaining its operation, FIG. 6A is a schematic plan view of a boot strap capacitor used in the present invention, and FIG. 6B is It is the schematic sectional drawing. 1 ... Substrate, 2 ... Field SiO ₂ film, 3 ... Gate insulating film, 4,5 ... Diffusion layer, 6, 7 ... Gate electrode.

 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-56-114198 (JP, A) JP-A-57-82284 (JP, A) JP-A-54-61429 (JP, A) Electronic material 18 [11 ] (1979-11) PP. 127-131 "High-speed 64K dynamic N-MOS memory"

Claims (2)

[Claims] 1. A pulse generating circuit, a delay circuit which receives an output pulse from the pulse generating circuit and forms a delay pulse thereof, a gate side electrode which receives the output pulse, and a diffusion layer side electrode which receives the delay pulse. Is provided between the MOS capacitance received by the MOS capacitor and the electrode on the diffusion layer side of the MOS capacitance and the ground potential of the circuit, and substantially in parallel with the parasitic capacitance formed in series with the MOS capacitance. The diffusion layer side electrode of the capacitor is commonly used as one of the source and drain electrodes,
The other source / drain electrode is formed so as to surround the diffusion layer of the MOS capacitor, and a timing pulse having a phase opposite to that of the delay pulse is supplied to the gate to turn on the parasitic capacitance charge circuit. A switch MOSFET that pulls out the bootstrap voltage to the ground potential side of the
A bootstrap circuit, which is characterized in that it is taken out from the connection point of the capacitor with the electrode on the gate side. 2. The bootstrap circuit according to claim 1, wherein the bootstrap circuit forms a word line selection timing pulse or a bit line selection timing pulse of a MOS memory.