JPH0682791B2 - Complementary semiconductor integrated circuit device - Google Patents
Complementary semiconductor integrated circuit deviceInfo
- Publication number
- JPH0682791B2 JPH0682791B2 JP61093621A JP9362186A JPH0682791B2 JP H0682791 B2 JPH0682791 B2 JP H0682791B2 JP 61093621 A JP61093621 A JP 61093621A JP 9362186 A JP9362186 A JP 9362186A JP H0682791 B2 JPH0682791 B2 JP H0682791B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- conductivity type
- mos transistor
- circuit device
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000295 complement effect Effects 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型半導体集積回路装置に関し、特に出力ト
ランジスタと電源配線との接続に関する。The present invention relates to a complementary semiconductor integrated circuit device, and more particularly to connection between an output transistor and a power supply wiring.
従来、例えば多ビット系の相補型MOSメモリ回路装置の
出力回路部のレイアウトパターンおよびその等価回路と
しては、第３図及び第４図に示すように、Ｐチャンネル
出力トランジスタ31のソース領域32とVCC電源のアルミ
配線33とが、又Ｎチャンネル出力トランジスタ34のソー
ス領域35とGND電源のアルミ配線36とがそれぞれオーミ
ック接続されている。一方出力端子用ボンディングパッ
ド37からはＰチャンネル出力トランジスタ31のドレイン
領域38には直接アルミ配線でオーミック接続されるがＮ
チャンネル出力トランジスタ34のドレイン領域39とはN+
拡散抵抗40を介してアルミ配線でオーミック接続されて
いた。Conventionally, for example, as a layout pattern of an output circuit part of a multi-bit complementary MOS memory circuit device and its equivalent circuit, as shown in FIGS. 3 and 4, as shown in FIGS. The aluminum wiring 33 for the CC power source, the source region 35 of the N-channel output transistor 34, and the aluminum wiring 36 for the GND power source are ohmic-connected. On the other hand, the output terminal bonding pad 37 is directly ohmic-connected to the drain region 38 of the P-channel output transistor 31 by aluminum wiring.
The drain region 39 of the channel output transistor 34 is N +
It was ohmic-connected with aluminum wiring via the diffusion resistance 40.
上述した従来の出力回路パターンレイアウト法ではVCC
電源用アルミ配線がＮチャンネル出力トランジスタのド
レイン領域上を通過する為ドレイン領域のN+拡散層を延
長して、トンネル配線を形成する必要がある。通常N+拡
散層の層抵抗は約50Ω／□程度あり、上述したトンネル
配線のパターンレイアウトでは、数十オームのトンネル
抵抗が形成されてしまい、出力電流，出力電圧，動作ス
ピード等の回路特性に悪影響を及ぼすという欠点があ
る。In the conventional output circuit pattern layout method described above, V CC
Since the aluminum wiring for power supply passes over the drain region of the N-channel output transistor, it is necessary to extend the N + diffusion layer in the drain region to form a tunnel wiring. Normally, the layer resistance of the N + diffusion layer is about 50 Ω / □, and in the above-mentioned tunnel wiring pattern layout, a tunnel resistance of several tens of ohms is formed, which causes circuit characteristics such as output current, output voltage, and operating speed. It has the drawback of having an adverse effect.
特に、複数の出力回路をもつ多ビット系相補型MOSメモ
リ回路装置では、GND,VCC両電源アルミ配線幅が太くな
り、このトンネル抵抗値が大きくなる。上述したトンネ
ル抵抗値を小さくする方法として、N+拡散層の幅を広げ
長さ／幅の比を小さくする方法があるが、端子容量の増
加やパターンレイアウト面積の制限から実現できず大き
な問題となる。In particular, in a multi-bit complementary MOS memory circuit device having a plurality of output circuits, the GND and V CC both power supply aluminum wiring widths become thick and the tunnel resistance value becomes large. As a method of reducing the tunnel resistance value described above, there is a method of widening the width of the N + diffusion layer and reducing the length / width ratio, but this is not a real problem due to an increase in terminal capacitance and a limitation on the pattern layout area. Become.
本発明は、出力回路の出力トランジスタのソース領域と
電源との接続にポリサイドによるトンネル配線を使用し
たものである。The present invention uses polycide tunnel wiring for the connection between the source region of the output transistor of the output circuit and the power supply.
本発明の相補型半導体集積回路装置は、複数の出力回路
を有する相補型半導体集積回路装置において、出力回路
を構成する出力トランジスタのソース領域と電源配線と
がポリサイド配線で接続されていることを特徴とする。A complementary semiconductor integrated circuit device according to the present invention is characterized in that, in a complementary semiconductor integrated circuit device having a plurality of output circuits, a source region of an output transistor forming an output circuit and a power supply wiring are connected by a polycide wiring. And
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は相補型MOSメモリ回路の出力回路レイアウトパ
ターンであり、第２図は第１図のトンネル抵抗を含む等
価回路である。Ｎチャンネル出力トランジスタ11のソー
ス領域12はGND電源用アルミ配線13に直接オーミック接
続される。一方Ｐチャンネル出力トランジスタ14のソー
ス領域15はタングステンポリサイドによるポリサイド配
線16によるトンネル配線を介して、VCC電源用アルミ配
線17にオーミック接続されている。出力端子用ボンディ
ングパッド18からはＮチャンネル出力トランジスタ11及
びＰチャンネル出力トランジスタ14のドレイン領域19,2
0へアルミ配線21,22によりそれぞれオーミック接続され
ている。FIG. 1 is an output circuit layout pattern of a complementary MOS memory circuit, and FIG. 2 is an equivalent circuit including the tunnel resistance of FIG. The source region 12 of the N-channel output transistor 11 is directly ohmic-connected to the aluminum wiring 13 for GND power supply. On the other hand, the source region 15 of the P-channel output transistor 14 is ohmic-connected to the V CC power supply aluminum wiring 17 through the tunnel wiring of the polycide wiring 16 of tungsten polycide. From the bonding pad 18 for the output terminal, the drain regions 19, 2 of the N-channel output transistor 11 and the P-channel output transistor 14 are connected.
Ohmic connection to 0 is made by aluminum wiring 21 and 22, respectively.
以上説明したように本発明は、出力トランジスタのソー
ス領域と電源線との接続にポリサイド配線を使用するこ
とにより、従来のN+拡散層配線を使用した場合と比較し
て、抵抗値を１桁以上小さくでき、従ってレイアウトパ
ターン面積の増加を必要とせず、出力電流，出力電圧及
び動作スピード等の回路特性改善に寄与する効果があ
る。As described above, the present invention uses the polycide wiring for connecting the source region of the output transistor and the power supply line, and thus has a resistance value of one digit compared with the case of using the conventional N + diffusion layer wiring. Therefore, the layout pattern area is not required to be increased, and there is an effect that it contributes to improvement of circuit characteristics such as output current, output voltage, and operation speed.
尚、本実施例ではポリサイド配線をＰチャンネル出力ト
ランジスタのソース領域とVCC電源用アルミ配線との接
続に使用したが、逆に、Ｎチャンネル出力トランジスタ
のソース領域とGND電源用アルミ配線の接続に使用して
も良い。又、ポリサイド配線にはタングステンの他にモ
リブデンやチタン等によるポリサイドを用いても良い。In the present embodiment, the polycide wiring is used to connect the source region of the P-channel output transistor and the aluminum wiring for the V CC power supply. Conversely, the polycide wiring is connected to the source region of the N-channel output transistor and the aluminum wiring for the GND power supply. You may use it. In addition to tungsten, polycide made of molybdenum or titanium may be used for the polycide wiring.
第１図は本発明の一実施例の出力回路のレイアウトパタ
ーン図、第２図は第１図の等価回路、第３図は従来の出
力回路のレイアウトパターン図、第４図は第３図の等価
回路図である。 11,34……Ｎチャンネル出力トランジスタ、 14,31……Ｐチャンネル出力トランジスタ、 12,35……Ｎチャンネル出力トランジスタのソース領
域、15,32……Ｐチャンネル出力トランジスタのソース
領域、13,36……GND電源用アルミ配線、17,33……VCC電
源用アルミ配線、18,37……出力端子用ボンディングパ
ッド、16……ポリサイド配線、40……N+拡散層配線。FIG. 1 is a layout pattern diagram of an output circuit of an embodiment of the present invention, FIG. 2 is an equivalent circuit of FIG. 1, FIG. 3 is a layout pattern diagram of a conventional output circuit, and FIG. 4 is a diagram of FIG. It is an equivalent circuit diagram. 11,34 …… N-channel output transistor, 14,31 …… P-channel output transistor, 12,35 …… N-channel output transistor source area, 15,32 …… P-channel output transistor source area, 13,36… … Ground power aluminum wiring, 17,33 …… V CC power aluminum wiring, 18,37 …… Output terminal bonding pad, 16 …… Polycide wiring, 40 …… N + diffusion layer wiring.
Claims (1)
ジスタと逆導電型のMOSトランジスタを含む相補型半導
体集積回路装置において、前記一導電型のMOSトランジ
スタの形成領域と前記逆導電型のMOSトランジスタの形
成領域のそれぞれのゲート電極の延在方向とは垂直方向
な一辺側に出力端と接続したアルミニウム配線からなる
出力配線と、前記一導電型のMOSトランジスタの形成領
域と前記逆導電型のMOSトランジスタの形成領域の他辺
側に設けられたアルミニウム配線からなる第１の電源配
線と第２の電源配線とを有し、前記一導電型のMOSトラ
ンジスタのドレイン領域と前記逆導電型のMOSトランジ
スタのドレイン領域はそれぞれ前記出力配線とアルミニ
ウム配線で接続され、前記一導電型のMOSトランジスタ
のソース領域は前記第１の電源配線とポリサイド配線で
接続されたことを特徴とする相補型半導体集積回路装
置。1. A complementary semiconductor integrated circuit device including a MOS transistor of one conductivity type and a MOS transistor of the opposite conductivity type which constitute an output circuit, wherein a formation region of the MOS transistor of the one conductivity type and the MOS transistor of the opposite conductivity type. An output wiring made of an aluminum wiring connected to the output end on one side perpendicular to the extending direction of each gate electrode in the transistor formation region, a formation region of the one conductivity type MOS transistor, and the opposite conductivity type It has a first power supply wiring and a second power supply wiring made of aluminum wiring provided on the other side of the formation region of the MOS transistor, and the drain region of the MOS transistor of one conductivity type and the MOS of the opposite conductivity type. A drain region of the transistor is connected to the output wiring by an aluminum wiring, and a source region of the one conductivity type MOS transistor is connected to the first power wiring. Complementary semiconductor integrated circuit device, characterized in that connected in Risaido wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61093621A JPH0682791B2 (en) | 1986-04-22 | 1986-04-22 | Complementary semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61093621A JPH0682791B2 (en) | 1986-04-22 | 1986-04-22 | Complementary semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62249472A JPS62249472A (en) | 1987-10-30 |
| JPH0682791B2 true JPH0682791B2 (en) | 1994-10-19 |
Family
ID=14087391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61093621A Expired - Lifetime JPH0682791B2 (en) | 1986-04-22 | 1986-04-22 | Complementary semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682791B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154554A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Complementary type insulated gate field effect semiconductor device |
-
1986
- 1986-04-22 JP JP61093621A patent/JPH0682791B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62249472A (en) | 1987-10-30 |
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