JPS61141246A - Channel continuity test method - Google Patents

Channel continuity test method

Info

Publication number
JPS61141246A
JPS61141246A JP26271684A JP26271684A JPS61141246A JP S61141246 A JPS61141246 A JP S61141246A JP 26271684 A JP26271684 A JP 26271684A JP 26271684 A JP26271684 A JP 26271684A JP S61141246 A JPS61141246 A JP S61141246A
Authority
JP
Japan
Prior art keywords
channel
equipment
communication path
incoming
outgoing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26271684A
Other languages
Japanese (ja)
Other versions
JPH0520020B2 (en
Inventor
Masataka Takano
高野 真隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26271684A priority Critical patent/JPS61141246A/en
Publication of JPS61141246A publication Critical patent/JPS61141246A/en
Publication of JPH0520020B2 publication Critical patent/JPH0520020B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/24Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To decrease the amount of hardware and to attain a complete fault bracketing test by making frame phases of signals transmitted to an incoming channel and an outgoing channel of a time division electronic exchange equal so as to apply loopback to the outgoing channel to the incoming channel. CONSTITUTION:The channel equipment A consists of an incoming channel equipment AU and an outgoing channel equipment AD, and a channel equipment B consists of an incoming channel equipment BU and an outgoing channel equip ment BD. An output signal of a pattern generator PG generating a continuity test signal is fed to a pattern checker PC via the equipment BD, the channel 10, the equipment AD, the channel 11, the equipment AU, the channel 12 and the equipment BU. Further, a channel 13 reflecting a test signal on the way of the channel 10 and returning it to the equipment BU is provided. The equip ment BU is provided with a selector 2 switching a signal from the channel 12 or 13 and inputting it to the checker PC. The frame phase of the signal transmitted through the channels 10, 12 are made equal by using an interface IF between the equipments AU and BU and an IF between the equipments AD, BD, the test signal from the PG is switched by the selector 2 at the occurrence of a fault to locate the fault to the incoming and outgoing channels.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は時分割電子交換機の通話路導通試験方法に係り
、特に通話路装置の障害切り分IK好適な通話路導通試
験方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication path continuity test method for a time-division electronic exchange, and more particularly to a communication path continuity test method suitable for fault isolation IK of a communication path device.

〔発明の背景〕[Background of the invention]

従来の通話路導通試験方法をtgs図を参照して説明す
る。
A conventional communication line continuity test method will be explained with reference to TGS diagrams.

第3図には2つの通話路装置A、Bが示されており、各
通話路装置A、Bは、夫々上り測道話路装置Aσ、Bσ
及び下り測道話路装置AD、BDで構成されている。そ
して、端末装置甲から送出されたデータ信号は、上り測
道話路装置Aa、Brr及び下り測道話路装置BD −
A!lを通りて、端末装置乙に伝送されるようになって
いる。また、従来の各通話路装置A、Bは、夫々装置内
に通話路折り返し機能を備えており、パターンジェネレ
ータ円からの試験信号を通話路装置B内にて折り返し、
または通話路装置入内にて折り返し、折り返した試験信
号をパターンチェッカーPCで検査するよ5になりてい
る。尚、符号1及び2は夫々位相合せ回路及びセレクタ
を示している。
Two channel devices A and B are shown in FIG. 3, and each channel device A and B is an upstream channel device Aσ and Bσ
and downlink route survey equipment AD, BD. The data signal sent from the terminal device A is transmitted to the uplink channel devices Aa, Brr and the downlink channel device BD-
A! The data is transmitted to the terminal device B through the terminal B. In addition, each of the conventional communication path devices A and B has a communication path return function within the device, and the test signal from the pattern generator circle is returned within the communication path device B.
Alternatively, the test signal is returned at the input of the communication path device and the returned test signal is inspected by the pattern checker PC. Note that numerals 1 and 2 indicate a phase matching circuit and a selector, respectively.

この従来の試験方法では、通話路装置内に設けたシフト
レジスタやメモリ等で構成した折り返し機構により試験
信号を折り返す為、ハード量が大きくなるという欠点を
持つ。更に、例えばB装置内にて折り返し導通試験を行
なって′″OK″となり、A装置内にて折り返し導通試
験を行なって”NG” となった場合でも、100 %
の確率で障害がA装置内に生じていると判断できないと
いう不具合がある。つまり、例えばB装置内の折り返し
点Pと、B装置から通話路に出る出力点Qとの間に存在
するハードに故障が生じていた場合には、これを検出で
きない。
This conventional test method has the disadvantage that the amount of hardware is large because the test signal is returned by a return mechanism constituted by a shift register, memory, etc. provided in the communication path device. Furthermore, even if, for example, a folded continuity test is performed in device B and the result is ``OK'', and a folded continuity test is conducted in device A and the result is ``NG'', the result will be 100%.
There is a problem in that it cannot be determined that a failure has occurred in device A with a probability of . That is, for example, if a failure occurs in the hardware that exists between the return point P in the B device and the output point Q from the B device to the communication path, this cannot be detected.

このように、従来の試験方法は、ハード量が大きく、し
かも障害切り分けを完全にできないという欠点を有して
いた。
As described above, conventional testing methods have the disadvantage that they require a large amount of hardware and cannot completely isolate faults.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ハード量を小さくシ、シかも完全な障
害切り分けを可能とする通話路導通試験方法を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a communication line continuity test method that requires only a small amount of hardware and can completely isolate faults.

〔発明の概要〕[Summary of the invention]

本発明では、通話路装置間の上り測道話路と下り測道話
路を伝搬する夫々の信号のフレーム位相を等しくし、下
り測道話路を伝搬する信号を上り測道話路に折り返して
該折り返し区間内に在る通話路装置の導通試験を行なう
In the present invention, the frame phases of the signals propagating on the uplink channel and the downlink channel between communication channel devices are made equal, and the signals propagating on the downlink channel are looped back to the uplink channel. Then conduct a continuity test on the communication path equipment located within the turnaround section.

このように、通話路装置内に折り返し機能を設ける必要
がない為、その分のハード量が減少し、通話路装置外に
おいて信号を折り返すようにしたので、障害の切り分け
が可能となる、〔発明の実施例〕 以下、本発明の一実施例を第1図及び第2図を参照して
説明する。
In this way, since there is no need to provide a loopback function within the communication path device, the amount of hardware is reduced accordingly, and since the signal is looped back outside the communication path device, failures can be isolated. Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第1図は、本発明による通話路導通試験方法を適用した
通話路装置の一実施例の接続構成図である。
FIG. 1 is a connection configuration diagram of an embodiment of a communication path device to which the communication path continuity testing method according to the present invention is applied.

通話路装置人は、上り測道話路装置AI7と下り測道話
路装置ADとで構成され、通話路装置Bは上り測道話路
装置B、と下り測道話路装置BDとで構成されている。
The communication channel device is composed of an upstream channel device AI7 and a downstream channel device AD, and the channel device B is composed of an upstream channel device B and a downstream channel device BD. has been done.

導通試験用の試験信号を発生するパターンジェネレータ
川の出力信号は、下り測道話路装置BDe通話路10.
下り測道話路装置AD1通話路11.上り測道話路装置
AV9通話路12.上り測道話路装置Bυを介してパタ
ーンチェッカPCに送出されるよう罠なっている。
The output signal of the pattern generator that generates the test signal for the continuity test is transmitted to the downlink channel equipment BDe channel 10.
Downlink channel device AD1 channel 11. Uplink channel equipment AV9 channel 12. The trap is configured so that it is sent to the pattern checker PC via the uplink channel device Bυ.

また、通話路10の途中から試験信号を折り返しこれを
上り測道話路装置BUに戻す通話路13を設けである。
Furthermore, a communication path 13 is provided which loops back the test signal from the middle of the communication path 10 and returns it to the upstream survey channel device BU.

上り測道話路装置Bv内には、通話路12または通話路
13からの信号を切り換えてパターンチェッカPCK入
力するセレクタ2を設けである。
A selector 2 is provided in the uplink channel device Bv for switching the signal from the channel 12 or 13 and inputting the signal to the pattern checker PCK.

上り測道話路装置AU 、B(lの図示しない装置間イ
ンターフェースと、下り測道話路装置AD −BDの図
示しない装置間インターフェースにより、各装置間の通
話路10.12を伝搬する信号のフレーム位相を、例え
ば第2図に示すように等しくし【おく。
The inter-device interfaces (not shown) of the uplink channel devices AU and B(l) and the device interfaces (not shown) of the downlink channel devices AD-BD allow the signals propagating on the communication path 10.12 between each device to be The frame phases are made equal, for example, as shown in FIG.

第2図に示した信号(通話路データ)は、1フレームを
52タイムスロツトで構成し、各タイムスロットは夫々
8ビツトで構成しである。そして、上り清適話路装置A
y−Bg間の通話路データのタイムスロットゼロ(TS
o)における先頭のビット0の位置と、下り測道話路装
置B、−AD間の通話路データのタイムスロットゼロ(
TS O)における先頭のビット0の位置とを等しくし
である。このように、フレーム位相を等しくすることは
、時分割方式を採用する電子交換機にあっては、容易に
行なうことができる。
In the signal (communication path data) shown in FIG. 2, one frame consists of 52 time slots, and each time slot consists of 8 bits. And upstream channel device A
Time slot zero (TS
o) and the time slot 0 (
The position of the first bit 0 in TSO) is set equal to the position of the first bit 0 in TSO). In this way, making the frame phases equal can be easily achieved in an electronic exchange that employs a time division system.

障害が発生して通話路装置人と通話路装置Bの障害切り
分けを行なう必要がある場合、フレーム信号(第2図)
に同期してセレクタ2を切り換え、パターンジェネレー
タ川からの試験信号を特定のタイムスロットのみ折り返
し、 PG−+BD−4Bσ→PCのルートで導通試験
を行なう。通話路装置人からの上り清適話路データと、
通話路装置Bからの下り清適話路データのどちらの位相
も等しいため、セレクタ2による切り換えが可能となり
、その結果が”■″の場合には、通話路装置人の通話路
障害であると判断できる。
If a fault occurs and it is necessary to isolate the fault between the communication path device and the communication path device B, a frame signal (Figure 2)
Switch selector 2 in synchronization with , return the test signal from the pattern generator only in a specific time slot, and perform a continuity test on the route PG-+BD-4Bσ→PC. Uplink channel data from the channel equipment person,
Since both phases of the downlink clear channel data from communication path device B are equal, switching by selector 2 is possible, and if the result is "■", it is determined that there is a communication path failure in the communication path device. I can judge.

導通試験結果が“NG”の場合は、通話路装置Bが障害
であると判断でき、この通話路装置Bを交換後に通話路
障害が起これば、前記通話路装置人も障害であったと判
断できる。
If the continuity test result is "NG", it can be determined that the communication path device B is at fault, and if a communication path failure occurs after this communication path device B is replaced, it is determined that the communication path device person is also at fault. can.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、障害発生時の通話路装置の掌害切り分
けが可能な為、時分割電子交換機の保守性の向上を図れ
る。また、通話路装置内ではなく、通話路装置間で折り
返す為、ハードウェアの部品が従来に比べて減少し、経
済性も向上する。
According to the present invention, since it is possible to isolate the damage to the communication path device when a failure occurs, it is possible to improve the maintainability of the time division electronic exchange. In addition, since the loop is looped between the communication path devices rather than within the communication path device, the number of hardware parts is reduced compared to the conventional method, and economical efficiency is also improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による通話路導通試験方法を適用した通
話路装置の一実施例の接続構成図、第2図は本発明方法
の一実施例を説明する通話路データの位相図、第3図は
従来の通話路導通試験方法を説明する通話路装置の接続
構成図である。 Ag + Bg・・・上り測道話路装置A3)、BD・
・・下り清適話路装置 甲、乙・・・端末装置 PG−・・パターンジェネレータ PC・・・パターンチェッカ ト・・位相合せ回路 2・・・セレクタ
FIG. 1 is a connection configuration diagram of an embodiment of a communication path device to which the communication path continuity test method according to the present invention is applied; FIG. 2 is a phase diagram of communication path data illustrating an embodiment of the method of the present invention; The figure is a connection configuration diagram of a communication line device for explaining a conventional communication line continuity test method. Ag + Bg... Upward survey channel device A3), BD.
・・Downstream channel equipment A, B・・Terminal device PG・・・Pattern generator PC・・Pattern checker・・Phase matching circuit 2・・Selector

Claims (1)

【特許請求の範囲】[Claims] 複数の通話路装置を備える時分割電子交換機において、
通話路装置間の上り側通話路と下り側通話路を伝搬する
夫々の信号のフレーム位相を等しくし、下り側通話路を
伝搬する信号を上り側通話路に折り返して該折り返し区
間内に在る通話路装置の導通試験を行なうことを特徴と
する通話路導通試験方法。
In a time-sharing electronic exchange equipped with a plurality of communication path devices,
The frame phases of the respective signals propagating on the uplink communication path and the downlink communication path between communication path devices are made equal, and the signals propagating on the downlink communication path are looped back to the uplink communication path so that the signals remain within the folding section. 1. A communication path continuity test method characterized by conducting a continuity test of a communication path device.
JP26271684A 1984-12-14 1984-12-14 Channel continuity test method Granted JPS61141246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26271684A JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26271684A JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Publications (2)

Publication Number Publication Date
JPS61141246A true JPS61141246A (en) 1986-06-28
JPH0520020B2 JPH0520020B2 (en) 1993-03-18

Family

ID=17379599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26271684A Granted JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Country Status (1)

Country Link
JP (1) JPS61141246A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758491A (en) * 1980-09-26 1982-04-08 Nec Corp Channel continuity test system for digital exchanger

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758491A (en) * 1980-09-26 1982-04-08 Nec Corp Channel continuity test system for digital exchanger

Also Published As

Publication number Publication date
JPH0520020B2 (en) 1993-03-18

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