JPS62232042A - Fault detecting system - Google Patents

Fault detecting system

Info

Publication number
JPS62232042A
JPS62232042A JP61074276A JP7427686A JPS62232042A JP S62232042 A JPS62232042 A JP S62232042A JP 61074276 A JP61074276 A JP 61074276A JP 7427686 A JP7427686 A JP 7427686A JP S62232042 A JPS62232042 A JP S62232042A
Authority
JP
Japan
Prior art keywords
operating system
normality
transferred
information
route
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61074276A
Other languages
Japanese (ja)
Inventor
Hisao Yagi
久雄 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61074276A priority Critical patent/JPS62232042A/en
Publication of JPS62232042A publication Critical patent/JPS62232042A/en
Pending legal-status Critical Current

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  • Monitoring And Testing Of Exchanges (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To heighten inspection the ability to the normality of information channel connecting a duplex device and a unitizing device by verifying information in two time slots for normality confirming signal in an operating system and a standby system. CONSTITUTION:A duplex device 1a has an operating system duplex device 1b as the standby system, and normality confirming signal adding circuits 16a, 16b and normality confirming signal examining circuits 17a, 17b are provided in these duplex devices 1a, 1b respectively. Controlling information 14 from a controller in the unitizing device 2 is transferred to selection circuits 6a, 6b, and normality confirming signals (A) 9a, 9b and a normality confirming signal (B) 12 are inserted to it and transferred to duplex devices 1a, 1b as return paths 4a, 4b of an information channel. Time slots (A), (B) 18a, 18b for normality confirming signal in the return paths of information channel are inspected respectively by normality confirming signal examining circuits 17a, 17b in the duplex devices 1a, 1b.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は障害検出方式に係り、特に運転系と予備系より
なる二重化された上位装置が冗長構成を臂しない下位装
置と時分割多重された情報路により接続され、その上位
装置の運転系と予備系の両系がそれぞれ下位装置と情報
路の往路・復路によυ情報の送受を行う方式における障
害検出方式に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a failure detection system, and in particular, a fault detection method in which a duplexed higher-level device consisting of an operating system and a standby system is time-division multiplexed with a lower-level device that does not have a redundant configuration. The present invention relates to a failure detection method in a system in which the operating system and the standby system of a higher-level device are connected by an information path and send and receive υ information to and from the lower-level device through the outbound and return paths of the information path.

〔従来の技術〕[Conventional technology]

従来のこの種の障害検出方式としては、時分割多重され
た情報路内に正常性確認信号用タイムスロットを1つ配
備し、二重化装置の運転系よシ付与されその運転系の往
路により転送されたものを下位[1を経由し運転系と予
備系の両方に返送する方式、あるいは、システムの平常
運転時には上述の方式を採り、システムの診断時には上
述した同じタイムスロットを使用し、運転系に付与され
た運転系の往路により転送されたものは運転系の復路に
返送し、予備系に付与された予備系の往路により転送さ
れたものは予備系の復路に返送する方式を合わせ持つシ
ステムが考えられていた。
Conventional fault detection methods of this type include one time slot for a normality confirmation signal in the time-division multiplexed information path, and a signal is assigned to the operating system of the duplexing device and transmitted by the outgoing path of the operating system. The method is to return the data to both the operating system and the standby system via the lower level [1], or the method described above is adopted during normal operation of the system, and the same time slot described above is used during system diagnosis, and the system is returned to the operating system. There is a system that has a system in which items transferred by the outgoing route of the operating system assigned to the operating system are returned to the return route of the operating system, and items transferred by the outgoing route of the backup system assigned to the backup system are returned to the return route of the backup system. It was considered.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の障害検出方式では、平常時においては運
転系により付与された正常性確認信号を運転系と予備系
の両系において検証するため、二重化装置の予備系よシ
ー重化装置へいたる経路の障害が検出さ九ず、かつ運転
系の往路・復路および予備系の復路における障害検出の
分解能が低いという間1点があった。
In the conventional fault detection method described above, in normal times, the normality confirmation signal given by the operating system is verified in both the operating system and the backup system, so the route from the backup system of the duplexing device to the sea duplexing device is One point was that no faults were detected, and the resolution of fault detection on the outbound and return routes of the operating system and the return route of the backup system was low.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の障害検出方式は、時分割多重された情報路内に
正常性確認信号用の第1および第2のタイムスロットを
配備し、上記第1のタイムスロットは二重化装置の運転
系に付与され、その運転系の往路により転送されたもの
を下位装置を経由し運転系と予備系の両方に返送し、上
記第2のタイムスロットは上記運転系に付与されその運
転系の往路により転送されたものはその運転系の復路に
返送し、予備系に付与されその予備系の往路により転送
されたものはその予備系の復路に返送し、上記二重化装
置の運転系と予備系の両系にて上記第1および第2の2
つの正常性確認信号用タイムスロット内の情報を検証す
る手段を備えてなるようにしたものである。
The fault detection method of the present invention provides first and second time slots for normality confirmation signals in a time-division multiplexed information path, and the first time slot is assigned to the operation system of the duplexing device. , the data transferred by the outgoing route of the operating system is returned to both the operating system and the standby system via the lower device, and the second time slot is given to the operating system and transferred by the outgoing route of the operating system. Items are sent back to the return route of the operating system, and items that are assigned to the backup system and transferred by the outbound route of the backup system are returned to the return route of the backup system. 1st and 2nd 2 above
The present invention includes means for verifying information within the two normality confirmation signal time slots.

し作 用〕 本発明においては、二重化装置と一重化装置間の時分割
多重された情報路内に配備した2つの正常性確認信号用
タイムスロットの1つのタイムスロットは上記二重化装
置の運転系に付与されその運転系の往路により転送され
たものを下位itを経由して運転系と予備系の両方に返
送し、他のタイムスロットは運転系に付与されその運転
系の往路により転送されたものは運転系の復路に返送し
、予備系に付与されその予備系の往路により転送された
ものは予備系の復路に返送し、二重化装置の運転系と予
備系の両系にて2つの正常f!E確認信号用タイムスロ
ット内の情報を検証する。
Function] In the present invention, one of the two time slots for normality confirmation signals provided in the time-division multiplexed information path between the duplexing device and the duplexing device is used for the operation system of the duplexing device. The time slots assigned to the operating system and transferred by the outbound route of the operating system are returned to both the operating system and the standby system via the lower IT, and the other time slots are assigned to the operating system and transferred by the outward route of the operating system. is returned to the return route of the operating system, and those assigned to the backup system and transferred by the outbound route of the backup system are returned to the return route of the backup system. ! Verify the information in the E confirmation signal timeslot.

〔実施例〕〔Example〕

以下、図面に基づき本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

図は本発明の一実施例を示すブロック図である。The figure is a block diagram showing one embodiment of the present invention.

図において、Ia、1bは二重化g&Rを示し、この実
施例では二重化装(jtla を運転系、二重化装置1
bを予備系とし、これら各二重化装置1a。
In the figure, Ia and 1b indicate duplex g&R, and in this embodiment, duplex equipment (jtla is the operation system, duplex equipment 1
b is a standby system, and each of these duplexing devices 1a.

1bにはそれぞれ正常性?il[!信号付加回路16a
Is each normality in 1b? il [! Signal addition circuit 16a
.

tab および正常性確認信号検査回路17a、17b
が設けられている。i5a、15bは制御情報路である
tab and normality confirmation signal inspection circuits 17a, 17b
is provided. i5a and 15b are control information paths.

2は一重化装置で、上記二重化装置1a、ibとこの一
重化装置間とはそれぞれ情報路往路3a。
Reference numeral 2 denotes a duplexing device, and information paths 3a are connected between the duplexing devices 1a and ib and this duplexing device, respectively.

情報路復路4aおよび情報路往路3b  、情報路復路
4bに接続されている。
It is connected to the information path return path 4a, the information path outbound path 3b, and the information path return path 4b.

そして、この−重化装置+t2は、正常性確認信号抽出
回路(A)5a、5b  と選択回路6a、6bおよび
運転系選択回路Tならびに正常性i認信号抽出回路(B
)8を含み構成される。9 a + 9 b  は正常
性確認信号用を示し、10a、10b、11.13.1
4は制御情報、12は正常性確認信号(B)を示す。
This -duplexing device +t2 includes normality confirmation signal extraction circuits (A) 5a, 5b, selection circuits 6a, 6b, operation system selection circuit T, and normality i confirmation signal extraction circuit (B).
)8. 9a + 9b indicates normality confirmation signal, 10a, 10b, 11.13.1
4 indicates control information, and 12 indicates a normality confirmation signal (B).

第2図は第1図における制御情報中の信号タイムスロッ
ト構成を示す図である。
FIG. 2 is a diagram showing the structure of signal time slots in the control information in FIG. 1.

この第2図において、18aは正常性確認信号用タイム
スロット(4)を示したものであり、18bは正常性N
u信号用タイムスロット(B)を示したものである。そ
して、0,1,2,16.30゜31はそれぞれデータ
用タイムスロットを示し、このデータ用タイムスロット
Oおよび16がそれぞれ正常性確認信号用タイムスロッ
ト18a+18bに対応する。
In this FIG. 2, 18a shows the time slot (4) for the normality confirmation signal, and 18b shows the normality confirmation signal time slot (4).
This shows the u signal time slot (B). 0, 1, 2, 16.30° 31 indicate data time slots, and data time slots O and 16 correspond to normality confirmation signal time slots 18a+18b, respectively.

つぎにこの第1図に示す実施例の動作を第2図を参照し
て説明する。
Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

まず、二重化装置1a、1b においては、正常性確認
信号検査回路15a、16b により制御情報路15a
、15b 中の正常性確認信号用タイムスロット囚、(
B)18a、18b (第2図参照)に正常性確認信号
を付原され、情報路往路3a 、3bに転送される。
First, in the duplexing devices 1a and 1b, the control information path 15a is
, 15b, the time slot for the normality confirmation signal, (
B) A normality confirmation signal is sent to 18a and 18b (see FIG. 2) and transferred to the outgoing information paths 3a and 3b.

一方、−重化装置2においては、情報路往路3a、3b
中よ)正常性確認信号検査回路囚5a。
On the other hand, in the -multiplexing device 2, the information paths 3a, 3b
Inside) Normality confirmation signal inspection circuit prisoner 5a.

5bによ!0、g2図にて18aとして示される正常性
確認信号用タイムスロット回申の情報を抽出し、正常性
確認信号cA) 9 a 、 9 b  として選択回
路6a、6bにそれぞれ転送され、情報路復路4a。
5b! The information on the time slot circulation for the normality confirmation signal shown as 18a in FIG. 4a.

4bの正常性確認信号用タイムスロットcA>18aに
挿入される。
4b is inserted into the normality confirmation signal time slot cA>18a.

つぎに、制御情報1(la、10bは運転系選択回路7
により運転系の情報だけが制御情報11として転送され
る。そして、この制御情報11を入力とする正常性確認
信号抽出回路(B)8により第2図にて18b として
示される正常性確認信号用タイムスロット(B)中の情
報を抽出し、正常性確認信号(B)12として選択回路
6a、6b にそれぞれ転送され、情報路復路4a、4
bの正常性確認I言号用タイムスロット(B) 18 
bに挿入される。そして、上記正常a確認信号抽出回路
(B)8からの制御情報13は一重化装置2内の制御装
置(図示せず)へ転送される。
Next, control information 1 (la, 10b is the operation system selection circuit 7
Therefore, only operation-related information is transferred as control information 11. Then, the normality confirmation signal extraction circuit (B) 8 which receives this control information 11 as input extracts the information in the normality confirmation signal time slot (B) shown as 18b in FIG. 2, and confirms the normality. The signal (B) 12 is transferred to the selection circuits 6a and 6b, respectively, and the return information path 4a and 4
Time slot for normality confirmation I language of b (B) 18
inserted into b. The control information 13 from the normal a confirmation signal extraction circuit (B) 8 is transferred to a control device (not shown) in the multiplexing device 2.

また、この−重化装置2内の図示しない制御装置からの
制御情報14は、選択回路6a、6bに転送され、上述
した手順で正常性確認信号(A)9a。
Further, control information 14 from a control device (not shown) in this multiplexing device 2 is transferred to selection circuits 6a and 6b, and a normality confirmation signal (A) 9a is generated in the above-described procedure.

9bおよび正常性r4認信号(B)12を挿入され、情
報路復路4a、4bとして二重化装置1a、1b  に
転送される。そして、この二重化装[1a、1b内にて
は正常性確認信号検査回路17a 、 17b によp
1情報路復路4m、4b 中の正常性m信号号用タイム
スロットcA) 、 (B) 18 a 、 18 b
 がそれぞれ検査される。
9b and a normality r4 recognition signal (B) 12 are inserted, and transferred to the duplexing devices 1a, 1b as information paths 4a, 4b. In this duplex system [1a, 1b, normality confirmation signal test circuits 17a, 17b are used]
1 Time slot for normality m signal in return path 4m, 4b cA), (B) 18a, 18b
are each examined.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、時分割多重され
た情報路内に正常性確認信号用タイムスロットを2つ配
備し、1つのタイムスロットハ二重化装置の運転系に付
与されその運転系の往路により転送されたものを下位装
置を経由し運転系と予備系の両方に返送し、他のタイム
スロットは運転系に付与されその運転系の往路により転
送されたものは運転系の復路に返送し、予備系に付与さ
れその予備系の往路により転送されたものは予備系の復
路に返送し、二重化装置の運転系と予備系の両系にて2
つの正常性確認信号用タイムスロット内の情報を検証す
る手段を備えることにより、二重化装置と一重化!!置
間を接aする情報路の正常性検査性能を高める効果があ
る。すなわち、運転系の往路と復路、予備系の往路と復
路を常時監視することができ、また、障害検出の分解能
を各情報単位に1で高めることができるので、実用上の
効果は極めて犬である。
As explained above, according to the present invention, two time slots for normality confirmation signals are provided in the time-division multiplexed information path, and one time slot is assigned to the operation system of the duplexing device. What was transferred on the outward route is returned to both the operating system and the standby system via the lower device, and the other time slots are given to the operating system, and what was transferred on the outward route of the operating system is sent to the return route of the operating system. What was sent to the backup system and transferred by the outbound route of the backup system is returned to the return route of the backup system, and is transferred to both the operating system and the backup system of the duplexing device.
By providing a means to verify the information in the two normality confirmation signal time slots, it can be combined with a duplex device! ! This has the effect of improving the normality inspection performance of the information path that connects the equipment. In other words, it is possible to constantly monitor the outbound and return routes of the driving system and the outbound and return routes of the backup system, and the resolution of failure detection can be increased by 1 for each information unit, so the practical effect is extremely simple. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2因は
第1図における制御情報中の信号タイムスロット構成を
示す図である。 1a ・・e・二重化装置運転系、1b ・・・・二重
化装置予備系、2・・・・−重化装置、3a、3b・・
・・情報路往路、4a、4b  ・・拳−情報路復路、
5a 、 5b  ・・・・正常性確認信号抽出回路(
4)、6a 、 6b  ・・・・選択回路、7・・・
・運転系選択回路、8・・・・正常性確認信号抽出回路
(E)、16a 、  16b  ・・・・正常性確認
信号付加回路、17a 、17b  ・・・Φ正常性確
認信号検査回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and the second factor is a diagram showing the signal time slot structure in the control information in FIG. 1. 1a...e-duplexing device operation system, 1b...duplexing device backup system, 2...-duplexing device, 3a, 3b...
...Information route outbound, 4a, 4b...Fist-Information route return,
5a, 5b... Normality confirmation signal extraction circuit (
4), 6a, 6b... selection circuit, 7...
- Operation system selection circuit, 8... Normality confirmation signal extraction circuit (E), 16a, 16b... Normality confirmation signal addition circuit, 17a, 17b... Φ Normality confirmation signal inspection circuit.

Claims (1)

【特許請求の範囲】[Claims] 運転系と予備系よりなる二重化された上位装置が冗長構
成を有しない下位装置と時分割多重された情報路により
接続され、該上位装置の運転系と予備系の両系がそれぞ
れ前記下位装置と情報路の往路・復路により情報の送受
を行う方式において、前記時分割多重された情報路内に
正常性確認信号用の第1および第2のタイムスロットを
配備し、前記第1のタイムスロットは二重化装置の運転
系に付与され該運転系の往路により転送されたものを前
記下位装置を経由し運転系と予備系の両方に返送し、前
記第2のタイムスロットは前記運転系に付与され該運転
系の往路により転送されたものは該運転系の復路に返送
し、予備系に付与され該予備系の往路により転送された
ものは該予備系の復路に返送し、前記二重化装置の運転
系と予備系の両系にて前記第1および第2の2つの正常
性確認信号用タイムスロット内の情報を検証する手段を
備えてなることを特徴とする障害検出方式。
A duplexed higher-level device consisting of an operating system and a standby system is connected to a lower-level device that does not have a redundant configuration by a time-division multiplexed information path, and both the operating system and the standby system of the upper-level device are connected to the lower-level device, respectively. In a method of transmitting and receiving information through an outbound and a return path of an information path, first and second time slots for normality confirmation signals are provided in the time-division multiplexed information path, and the first time slot is The time slot assigned to the operating system of the duplexing device and transferred by the outbound route of the operating system is returned to both the operating system and the standby system via the lower-level device, and the second time slot is assigned to the operating system and transferred to the operating system. What was transferred by the outbound route of the operating system is returned to the return route of the operating system, and what was assigned to the backup system and transferred by the outbound route of the backup system is returned to the return route of the backup system, A fault detection system characterized by comprising means for verifying information in the first and second normality confirmation signal time slots in both the system and the backup system.
JP61074276A 1986-04-02 1986-04-02 Fault detecting system Pending JPS62232042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61074276A JPS62232042A (en) 1986-04-02 1986-04-02 Fault detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61074276A JPS62232042A (en) 1986-04-02 1986-04-02 Fault detecting system

Publications (1)

Publication Number Publication Date
JPS62232042A true JPS62232042A (en) 1987-10-12

Family

ID=13542426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61074276A Pending JPS62232042A (en) 1986-04-02 1986-04-02 Fault detecting system

Country Status (1)

Country Link
JP (1) JPS62232042A (en)

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