JPS6374358A - Speech path usually testing method - Google Patents

Abstract

PURPOSE:To detect even the fault of multi-connection by setting a semi fixed bus to a test time slot and adding the parity of inverse logic to a prescribed logic at the incoming side of a speech path as to the test data inserted thereto and checking the parity at the outgoing side by inverse logic. CONSTITUTION:In an incoming highway 16 from a subscriber circuit, when a timing signal 1 takes place in a prescribed timing to a control input 30 from a timing generating circuit 32 by a fixed time slot insertion circuit 24, a test pattern generated by a test pattern generating circuit 28 is inserted to the test time slot specified in the highway. Then it is transformed into a parallel data by a serial-parallel transforming circuit and a parity generating circuit 34 together with the serial data of the time slot of other usual talking and the result is inputted to a line concentration switch 10. In such a case, an odd parity is added at the time slot of the usual talking data and an even parity is added at the test time slot. In the parallel high way, the call is exchanged by the switch 10, a distribution switch 12 and a relay switch 14 and an odd parity is checked by a parallel/serial transforming circuit and a parity check circuit 68.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for constantly testing a communication path, and more specifically, to a method for constantly testing a communication path device of a digital exchange.

(Prior Art) Conventionally, for the constant testing of the communication line equipment of a digital exchange, for example, the "Digital Switch [IV] Hardware Applications (l)" published by Nippon Telegraph and Telephone Corporation, Volumes 24 to 28.4 are used.
There is a method described on page 8.86.37. In this conventional system, circuits for parity check tests and pilot tests are provided on the incoming and outgoing highways of the subscriber line exchange between the subscriber equipment and the relay station. More specifically, in order to confirm the normality of the path setting of the communication path equipment, which consists of communication path switches arranged in the order of concentrator switch, distribution switch, and relay switch in the direction from the subscriber circuit to the relay station, parity Two types of tests are constantly being conducted: check tests and pilot tests.

In the up-highway parity check test, a parity creation circuit is installed on the input side of the concentrator switch, and a parity check circuit is installed on the output side of each of the concentrator switch, distribution switch, and relay switch. This is done by checking with the latter whether or not it has been received. Similarly, in the down-highway parity check test, a parity generation circuit is installed on the input side of the relay switch, and a parity check circuit is installed on the output side of each switch, and the normality of the parity generated by the former is checked by the latter. This is done by doing this. This allows inspection of the bit stack of the communication path, abnormalities in the communication path memory, and the like.

The pilot test was conducted as follows. For uplink highways, there is a test pattern creation circuit before the parity creation circuit on the input side of the concentrator switch, and a fixed time slot insertion circuit that inserts the test pattern into the fixed time slot of the highway, and a fixed time slot insertion circuit on the output side of the relay switch. After the parity check circuit, a fixed time slot extraction circuit for extracting a test pattern from the fixed time slot of the highway and a test pattern check circuit are provided, respectively. Regarding the down highway, a test pattern generation circuit and a fixed time slot insertion circuit are installed before the parity generation circuit on the input side of the relay switch, and a fixed time slot extraction circuit and test circuit are installed after the parity check circuit on the output side of the concentrator switch. A pattern check circuit is provided for each.

Therefore, when starting up a call route, a semi-fixed call path is set up and connected between the fixed time slot for entrance tests and the fixed time slot for exit tests of each highway, and the test pattern is always on. Checks were conducted to monitor whether there were any abnormalities in the call path connection.

(Problems to be Solved by the Invention) However, such conventional systems have the following problems. First, multiple connections at each switch could not be detected. In other words, an abnormal connection state in which one incoming time slot is output to multiple outgoing time slots due to an incorrect connection cannot be detected. This is because no monitoring is performed.

Second, as the number of highways increased, the necessary hardware, such as fixed time slot extraction circuits and test pattern checking circuits, had to increase accordingly.

Therefore, the amount of hardware increases according to the number of highways.

Thirdly, in the pilot test, since the fault detection unit is the range from the test pattern insertion position on the input side to the test pattern detection position on the output side, there is a drawback that the resolution of failure detection is low. In other words, it was not possible to pinpoint the fault location in detail beyond that range.

Finally, since the failure detection points in the parity check test and the pilot test are different, the amount of hardware and software processing is large.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a method for constantly testing a communication path that can more appropriately confirm the normality of the communication path with a simple configuration.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention establishes parity between the input side and the output side of the communication path switch using a predetermined logic for highway time slot data. The call path continuous testing method, which constantly tests the call path of a digital exchange that is added and inspected and then replaced with a highway, is to allocate a test time slot to a fixed time slot on the highway and half the connection path to the call path switch. The test data is fixedly set and a predetermined pattern of test data is inserted into the test time slot on the input side of the channel switch.For the test data, a parity with a logic opposite to the predetermined logic is set at the input side of the channel switch. In addition, on the output side of the communication path switch,
The parity of the test data is checked using reverse logic.

(Function) According to the present invention, a semi-fixed path is set in the communication path,
A test pattern is inserted into the test fixed time slot on the input side of the communication path.0 In the parity generation circuit on the input side of the communication path, a parity with a logic opposite to that of other time slots is added to the test fixed time slot. A parity check circuit on the output side of each switch in the communication path performs a parity check using reverse logic for the fixed time slot for testing. This results in a constant test that combines a parity check test and a pilot test.

(Example) Next, an example of the communication channel constant testing method according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, in an embodiment of the present invention, a subscriber line intersection between a subscriber unit and a relay station! ! ! ! On the plane, press the east line switch 10. A constant test combining two types of parity check tests and pilot tests is performed on the communication path device consisting of the distribution switch 12 and the central switch 14 to confirm the normality of the communication path setting.

The upstream highway (HW) 1B from the subscriber circuit is basically the upstream highway 18 to the relay station via the concentration switch lO1 distribution switch 12 and the relay switch 14.
connected to. Similarly, down highway 2 from the relay station
0 is the downstream highway 2 to the subscriber circuit through the relay switch 14, the distribution switch 12 and the east line switch 10.
Connected to 2.

The upstream highway 16 from the subscriber circuit is a serial transfer highway, which includes a fixed time slot (TS).
An insertion circuit 24 is provided. The fixed time slot insertion circuit 24 has the upstream/% Iway 1B inserted into one input, and the output of the test pattern creation circuit 28 is connected to the other input 2B. Fixed time slot insertion circuit 2
Reference numeral 4 denotes a selection circuit that inserts the test pattern created by the test pattern creation circuit 28 into the test time slot in response to the timing signal (2) supplied from the timing creation circuit 32 to the control input 30. In this embodiment, the test pattern is, for example, hexadecimal number r55. A predetermined pattern of alternating AAJs is advantageously used.

The upstream highway 16 from the subscriber circuit is also provided with a serial/parallel converter circuit and a parity generator circuit 34 after the fixed time slot inserter circuit 24, whose 8-bit output 3
B is housed in the concentrator switch 10. The serial/parallel conversion circuit and parity generation circuit 34 is a circuit that converts an input serial transfer highway into a parallel transfer highway and generates a predetermined parity bit (P) according to the highway data. In this embodiment, the parity generation period is normally odd parity, and even parity is used only in the test time slot. Parallel 9-bit highways are exchanged in the concentrator switch lO1 distribution switch 12 and the relay switch 14.

The parity output 3B is the exclusive OR (EOR) circuit 4
Connected to one input of 0. The other input 42 of the EOR circuit 40 receives the timing signal ■ from the timing generation circuit 32 . Output 4 of EOR circuit 40
4 is input to the east line switch 10 along with the 8-bit output 3B from the serial conversion circuit and parity creation circuit 34.

A parity check circuit 50, an EOR circuit 52, and a parity error flip-flop (F/F) 54 are connected to the upstream highway 46 from the concentrator switch IO as shown in the figure. Similarly, a parity check circuit 50, an EO
R circuit 58 and parity error flip-flop 80
are connected as shown.

Parity check circuits 50 and 56 are circuits for checking parity errors on the parallel 9 bits of uplink highways 46 and 48, respectively, with odd parity normally, and with even parity in the case of test time slots.
Inputs 62 and 64 of EOR circuits 52 and 58 include
Timing signals ■ and ■ from the timing generation circuit 32
are input respectively. Parity error free flip-flops 54 and 60 are flip-flops that are set when a parity error occurs to indicate that fact.

A parallel-to-serial conversion circuit and a parity check circuit 68 are connected to the upstream highway 6B on the output side of the relay switch 14, and the circuit B8 detects the parity bit included in the 9-bit parallel highway 86 and performs an odd parity check. This circuit also converts the remaining parallel 8 bits into serial data and outputs it as an 8-bit serial highway 18 to the relay station. When an error occurs in parity, an error output PE is output. For parity error output cuff 0,
An EOR circuit 72 similar to EOR circuit 58 and a parity error flip-flop 74 similar to parity error flip-flop 60 are connected as shown. The input cuff 6 of the EOR circuit 72 receives the timing signal ■ from the timing generation circuit 32 .

Similarly, the downlink highway 20 from the relay station is also a serial transfer highway, but it is provided with a fixed time slot insertion circuit BO and a test pattern generation circuit 82 as shown. Fixed time slot insertion circuit 8
Reference numeral 2 designates a selection circuit similar to the fixed time slot insertion circuit 24, in which a test pattern is created in the test time slot by the test pattern creation circuit 82 in response to the timing signal 2 supplied from the timing creation circuit 32 to the control input 84. Insert test pattern.

Also, on the downlink highway 20 from the relay station, a serial-to-parallel conversion circuit and a parity creation circuit 8B similar to the serial-to-parallel conversion circuit and parity creation circuit 34 are arranged after the fixed time slot insertion circuit 80, and its 8-bit output 8 The day is stored in the relay switch 14.

Its parity output 92 is connected to one input of the EOR circuit 80. The other input 84 of the EOR circuit 82 receives the timing signal {circle around (2)} from the timing generation circuit 32 . The output 96 of the EOR circuit 40 is the 8-bit output 88 from the serial conversion circuit and parity creation circuit 8B.
The signal is also input to the relay switch 14.

Parity check circuits 102 and 104. EOR circuits 108 and 108. and parity error flip-flop 1
10 and 112 are connected as shown. These are the same as those for upbound highways 4B and 48. Timing signals ■ and ■ are input from the timing generation circuit 32 to inputs 114 and 11B of the FOR circuits 10B and 108, respectively.

On the downbound highway 118 on the exit side of the east line switch 10,
A parallel-serial converter and parity check circuit 120 is connected, and is a circuit similar to parallel-serial converter and parity check circuit 68. The parity error output 122 includes a FOR circuit 12 similar to the FOR circuit 106.
4. and a parity error flip-flop similar to parity error flip-flop 110.
re h7 +-1-1l-2 1- admittedly-V
M -r l-% 1 ffn (1 circuit 1
The timing signal [phase] is inputted from the timing generation circuit 32 to the input 128 of 24.

The timing generation circuit 32 generates timing signals ~[
This is a circuit that generates a phase with a timing as illustrated in FIG. 2, for example. In this embodiment, the test time slot is fixed and occupies 8 bits of time for l time slot.

The uplink highway 16 from the subscriber circuit is first inputted to the fixed time slot insertion circuit 24 in the uplink highway 18, and when the timing signal ■ of 8 pins If is generated at a predetermined timing from the timing generation circuit 32 to the control human power 30, this is done. The test pattern created by the test pattern creation circuit 28 is inserted into the specified test time slot of the up highway 18. For this test pattern, a hexadecimal alternating pattern such as "55, AAJ" is used.
The data is converted into parallel data and input to the concentrator switch IO.

At this time, a parity bit is outputted to the parity output 38 of the circuit 34 as odd parity. This is input to the FOR circuit from one input of the EOR circuit 40, and is output to its output 44 as odd parity when the timing signal 2 at the other input 42 is not significant, ie, in a normal speech data time slot. However, when the timing ■ is significant, that is, the odd parity of the circuit 34 is not output in the test time slot, so the even parity is added to the input highway 36 of the concentrator switch 10 from the output 44 of the EOR circuit 40.

To summarize, odd parity is added to normal call data time slots, and even parity is added to test time slots. Of course, in a system that uses even parity for normal time slots, it is sufficient to apply odd parity to test time slots.In short, for test time slots, parity is set using the opposite parity logic to other time slots. Add and inspect.

In any case, a 9-bit parallel highway including parity is input to the input side of the concentrator switch 10. This parallel highway includes a concentration switch 10 and a distribution switch 12.
The signals are exchanged at the relay switch 14 and input to the parallel-to-serial conversion circuit and parity check circuit 68. Same circuit 6
An odd parity check is performed at 8, and the data bits are converted to an 8-bit serial highway 18 and output to the relay station.

By the way, in this embodiment, a semi-fixed path is set for the test time slot. In other words, the timings of the test time slots on the output sides of the concentrator switch 10, distribution switch 12, and relay switch H are fixed. The timing generation circuit 32 generates timing signals (1) to (2) in accordance with the fixed timings of these switches.

Parity check circuits 50.5B and 68 check data on uplink highways 48, 48 and 66, respectively, for odd parity. When a parity error occurs, ie even parity is detected, their outputs 130, 132 or 70, ie the inputs of one of the EOR circuits 52, 58 or 72, are enabled. At that time, when the corresponding one of the timing signals 62, 64 or 7B of the other inputs 62, 64 or 7B of those EOR circuits is not significant (for example, high level), in other words, In a normal time slot, the corresponding parity error flip-flops 54, 60 and 74 are set.

However, if the corresponding one of the timing signals ■ to ■ of the other inputs 62, 64 and 7B of these FOR circuits becomes significant, that is, in the test time slot, the parity check circuit 50, 58 or 72 detects an even number. Even if parity is detected, the outputs of their EOR circuits are not activated, so parity error flip-flops 54
．． 60 and 74 are not set to 0. Conversely, if odd parity is detected in their parity check circuits, then a significant timing signal causes the parity error flip-flops 54.60 and 74 to be set to zero.
The corresponding one is set and a parity error is displayed.

As we will see, on the uplink highway of this communication path device, in normal time slots for calls, a parity error will be displayed if these parity check circuits check out odd parity, but in test time slots, even parity will be displayed. An error is displayed in parity.

The same applies to the down-highway from the relay station to the subscriber circuit. Although a detailed explanation thereof will be omitted, the test pattern inserted into the fixed test time slot by the fixed time slot insertion circuit 80 has even parity, and the other normal time slots have odd parity. Parity checking is performed in parity check circuits 102, 104 and 120, with even parity for test time slots and odd parity for regular time slots. The error display is
FOR circuits 108.108 and 128., respectively. and parity error flip-flops 110, 112 and 12B. These operations are performed using the timing signals ■~[phase] created by the timing creation circuit 32.
defined by.

As described above, in this embodiment, on the output side of each switch 1O112 and 14, even parity is checked for test time slots, and odd parity is checked for normal time slots. Therefore, in addition to a failure in which two test time slots are not switched, it is possible to detect a multi-connection failure in which a plurality of test time slots are output to the output side of these switches.

An example of a conventional communication path testing device is shown in FIG. 3, in which the same components as in FIG. 1 are designated by the same reference numerals. In this conventional method, the uplink highway parity check test is performed using a parity generation circuit 34 on the input side of the concentrator switch 10, and a parity check circuit 50 on the output side of each of the concentrator switch 10, the distribution switch 12, and the relay switch 14. , 5El and 68 are provided respectively, and parity check circuits 50 and 58 check whether the parity created by the parity creation circuit 34 has been received normally.
This is done by testing at 68 and 68. Similarly, for the down highway parity check test, a parity generation circuit 86 is provided on the input side of relay switch H, and parity check circuits 102, 104 and 120 are provided on the output side of each switch 14, 12 and 10, respectively. This is done by checking the normality of the created parity using the latter. These parity checks are performed using the same odd parity for both normal time slots and test time slots.

In this conventional method, the buy-low test was conducted as follows. For the up-bound highway, turn on the line concentration switch 1.
0 input side and a test pattern generation circuit 28 before the parity generation circuit 34, and a fixed time slot insertion circuit 2 for inserting the test pattern into a fixed time slot of the highway.
Further, after the parity check circuit 88 on the output side of the relay switch 14, a fixed time slot extraction circuit 200 for extracting a test pattern from the fixed time slot of the highway and a test pattern check circuit 202 are provided, respectively. Regarding the down highway, a test pattern creation circuit 82 and a fixed time slot insertion circuit 80 are provided before the parity creation circuit 8B on the input side of the relay switch 14, and a parity check circuit 120 is provided on the output side of the concentrator switch IO. A fixed time slot extraction circuit 204 and a test pattern check circuit 206 are provided afterwards.

In the pilot test, when starting up the communication path equipment, a semi-fixed communication path is set up and connected between the fixed time slot for ingress test and the fixed time slot for egress test of each highway. , the test pattern was checked to monitor whether there were any abnormalities in the call path connection.

Compared to this conventional method, the embodiment of the present invention does not require a fixed time slot extraction circuit or a test pattern check circuit, and even if the number of switches increases due to expansion,
It is only necessary to increase the output timing signal of the timing generation circuit, and the amount of hardware is reduced. Further, regarding the pilot test, since switching errors can be detected for each switch, the decomposition 71 for fault isolation is high.

Furthermore, since the failure points for the parity check test and the pilot test are the same, the amount of hardware is small.
Software processing is also simple. Furthermore, in this embodiment, since the parity check circuit and its EOR circuit selectively use both odd parity and even parity to check, it is possible to detect a stack of the parity check circuit.

(Effects of the Invention) In this way, in the present invention, on the output side of each switch, the parity check rules are different between the test time slot and the normal time slot, so not only the switching failure of the test time slot but also the multi-connection failures can also be detected. Additionally, the amount of hardware is reduced compared to conventional methods, and the resolution of fault isolation is high for pilot tests.

Furthermore, since the failure points in the parity check test and the pilot test are the same, the amount of hardware is small and the software processing is simple. It is also possible to detect a stuck parity check circuit.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment in which the present invention is applied to a subscriber line exchange located between a subscriber equipment and a relay station, and FIG. 2 shows signals appearing in each part of the embodiment shown in FIG. FIG. 3 is a functional block diagram similar to FIG. 1 illustrating an example of a conventional communication path constant test method. Explanation of symbols of main parts 10.12. , switches 16.18. ,Highway 24, ,Fixed time slot insertion circuit 2B, ,Test pattern generation circuit 32, ,Timing generation circuit 34, ,Serial to parallel conversion circuit and parity generation circuit 40.52. , exclusive OR circuit 54.60. , parity error flip-flop 88
Parallel-serial conversion circuit and parity check circuit Patent applicant: Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Corporation Agent: Writer: Takao Sakiyama

Claims (1)

[Claims] 1. A digital switching system in which highway switching is performed by adding parity and checking data in highway time slots according to a predetermined logic between the input side and output side of a communication path switch. In the call route constant testing method for constantly testing the call route, the test method includes: allocating test time slots to fixed time slots on the highway, semi-fixably setting connection paths in the call route switch; Insert test data of a predetermined pattern into the test time slot on the input side of the communication path switch, add parity of logic opposite to the predetermined logic to the test data on the input side of the communication path switch, A communication path constant testing method characterized in that, on the output side of a communication path switch, parity of the test data is checked using the inverse logic. 2. In the test method according to claim 1, the communication path switch includes a plurality of cascaded switches, and the parity check is performed at the output side of each of the plurality of switches. A continuous test method for communication channels.