JPH0437294A - Continuity test system - Google Patents

Abstract

PURPOSE:To test the normality of time switches and to reduce a time switch test time by comparing path setting of two time switches. CONSTITUTION:The same data is written to two highways HWI00-HWI0n, HWI10-HW1n, the data is read out of the same channel and data from two time switches 2, 3 are compared by data comparator circuits (0)4, (n)5 to reduce the check time of the time switches 2, 3. That is, when data written in the two highways are read in the same channel and if one highway is faulty, the read data are unmatched and the fault is discriminated. Moreover, the data are compared between different highways of the time switches 2, 3 then the possibility of finding out a fault caused in a common part of the one time switch 2 is increased. Thus, data of all channels are compared continuously and the test time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a continuity test method for a time-division communication path, and more particularly to shortening the test time of a device having a plurality of time switches.

[Conventional technology]

The conventional continuity test method is based on the Digital Switching System [N] Hardware Application (1) (1, 2) published by Nippon Telegraph and Telephone Corporation.
As described in Chapter Time-sharing Connector Device (pages 55 to 61), the test was conducted by interrupting the highway from the test device. FIG. 6 shows a schematic diagram of the conventional test method. The test pattern created by the test pattern generation circuit 8 is inserted into the incoming highway of the time switch 9 to be tested by the insertion circuit 10, and outputted to the highway to be tested in HW○0 to HWOn of the outgoing highway. The input side data and the output side data are compared by the data comparison circuit 12 via the selector 11, and if they are the same, it is determined that there is continuity. However, if it is a continuity test for one highway, it can be done in a short time, but when testing all the channels of the time switch as in the initial test, as shown in Figure 7, the inlet O-n channel and the output The test is performed by exchanging the O-n channels on the side, requiring nXn pass settings and data comparisons, and there is a problem that the test time increases as the capacity increases.

[Problem to be solved by the invention]

The above-mentioned conventional technology has a problem in that it has only one check circuit and is unable to improve test efficiency.

Furthermore, in the case of a time switch with 1024 channels, for example, it takes time for path setting and check protection for 1024 channels, and there is a problem in that most of the continuity test is a test of the time switch.

An object of the present invention is to shorten the continuity test time by shortening the time switch test time.

[Means to solve the problem]

In order to achieve the above object, the same data is written to two highways, read out on the same channel, and the data from the two time switches are compared to shorten the time switch check time.

[Effect]

If data written on two highways are read out to the same channel, and one of the highways is a fault, the read data will not match and it can be determined that there is a fault. It is not possible to determine which part of the highway is at fault, but if it is recognized as a fault, the only way to recover from the fault is to replace it with a spare package, so there is no need to do so.

Furthermore, by comparing the highways of different time switches, there is a high probability that a fault occurring in a common part of one time switch will be discovered.

Therefore, by using this time switch comparison method, all channels can be compared continuously, and the test time can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Except during testing, the input highways HW100 to HWI○n are time-converted by the time switch (o)2 and connected to the channel of the output highway HWOOO"HWOOn. Also, the input highways HW100 to HWI○n are connected to the channels of the output highway HWOOO"HWOOn. 1 n
is configured to be time-converted by time switch (1) 3 and connected to the channels of output highways HWO 10 to 1n, and time switch (0) 2 and time switch (1) 3 each constitute a time switch for a separate highway. There is.

Note that in one embodiment, the time switch highway is in serial form at a speed of 32 MHz.

During the test, the pattern data generation circuit 1 shown in Fig. 2 generates AA, 55 AA, and A test pattern insertion circuit generates repeating pattern data, inserts the pattern data into all channels of the highway, and sends the same data to two time switches. Furthermore, in time switch control, time switch (O) 2 and time switch (1) 3 are controlled in the same way, and the test pattern is that time switch (o) 2 and time switch (1) 3 are connected to the same channel on the same highway. I'll do it like that. As a result, the same data is output from the two time switches because the input data and time conversion are the same. FIG. 4 shows the data comparison circuit (m) 7 at the output highway m. The data comparison circuit only needs to simply compare data, and has a circuit configuration in which the output highways of the time switch (0) 2 and the time switch (1) 3 are simply compared by exclusive OR.

Figure 5 shows an example of unmatched pressure detection on M Highway. This figure shows the unmatched output when a time switch memory failure occurs in bit 1 of channel 0 of time switch 1, and the data that should be II I II becomes 11011. Since the data is "1" and the HWO1m data is O, the exclusive OR of both data results in an unmatched "1". When reading the unmatched data, monitoring starts when all the time switch path settings are completed, and the time switch is set to 55. Monitoring is performed between two frames in which both AA patterns are written and read, and if an unmatch occurs even once, it is determined to be a failure. Therefore, with this method, it is possible to complete the continuity test in the time equivalent to path setting + 2 frames, and the higher the capacity, the faster the test time will be reduced compared to the conventional configuration. Become.

Furthermore, in the configuration of the present invention, whether the input/output of the time switch is serial or parallel has no effect at all because the comparison is made in bit units on the output highway.

Also, AA of a specific channel on the outgoing highway side.

A test data insertion circuit inserts pattern data into a specific channel during non-testing, and the normality of the pattern is constantly monitored by the detection circuit after it passes through a time switch. is possible.

In this embodiment, the time switches are configured in one stage, but even in a communication system in which multiple stages of time switches are connected in series, each time switch can be controlled in the same manner as in the above embodiment. It is possible to conduct a continuity test of the entire system in a short time.

Further, in this embodiment, the comparison is made between highways with different time switches, but it goes without saying that comparison between highways with the same time switch is also effective.

〔Effect of the invention〕

According to the present invention, the normality of a time switch can be tested by comparing the path settings of two time switches, which is effective in shortening the time switch test time.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows a pattern data generation circuit, Fig. 3 shows pattern data contents, Fig. 4 shows a data comparison circuit, Fig. 5 shows an example of data comparison, and Fig. 6 shows a conventional Continuity test configuration, Figure 7 is an image diagram of time exchange. 1... Pattern data generation circuit. 2. Time switch (0), 3. Time switch (1),
4 Data comparison circuit (0), 5... Data comparison circuit (n), 6... Test pattern insertion circuit, 7... Data comparison circuit, 8... Pattern data generation circuit, 9... Time Switch, 10...Test pattern insertion circuit, 11...Selector. γ57 2nd Ryo Kuchi'5th Shoutaku δ Prisoner Anmapuke 1st Otsuguchi Yukuni? It's time, te

Claims (1)

[Claims] 1. A test data insertion circuit, a test data generation circuit that generates the test data, and a comparison circuit that compares two different highway data on the outbound highway of the time switch. and during testing, the test data insertion circuit inserts the same data into all time slots of a pair of highways, and the time switch controls the test data to be read out onto the two same highways, and the read data is read out. A continuity test method characterized in that a comparison is made using the comparison circuit. 2. The continuity test method according to claim 1, wherein a plurality of stages of time switches are interposed between the test data insertion circuit, the test data generation circuit, and the comparison circuit to perform the same continuity test. Continuity test method. 3. The continuity test method according to claim 1, wherein the test data is inserted only into a specific time slot when not testing. 4. The continuity test method according to claim 1, wherein the read data is compared between different time switches.