JPH10229430A - Continuity test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm normality of plural devices and to specify a faulty part in a failure state by writing simultaneously the same fixed data that does not change in each frame into all the time slots of the incoming highway of a speech path device from a test data generation circuit and then reading those fixed data, via an outgoing highway to compare them with the data sent from the test data generation circuit. SOLUTION: Test patterns produced by a test pattern data generation circuit 1 are simultaneously inserted to all of the time slots of the incoming highway of a time switch via a test pattern insertion circuit 6, and the same data are sent to two time switches. The outputs of both time switches are compared with the test patterns sent from the circuit 1 by a circuit, which performs comparison in all time slots with an exclusive OR. When it is notified that the comparison result shows a continuity test state by a TST signal, a gate opens and the comparison result can be read. Thus, the continuity test time is shortened, and also the demarcation of a faulty part is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a continuity test method for a communication path device, and more particularly to a continuity test method suitable for shortening a test time of a communication path device and identifying a failure point.

[0002]

2. Description of the Related Art A conventional continuity test system is disclosed in Japanese Patent Publication No. 5-260.
As described in Japanese Patent Publication No. 172, the test was performed by comparing two or three different highway data of the outgoing highway of the communication path device. The communication path device in this case is a time switch. FIG. 7 is a schematic diagram showing a case where three highway data are compared by a conventional test method. The test pattern created by the pattern data generation circuit 8 is inserted into the input highway of the time switch (0) 9, time switch (1) 10, and time switch (2) 11 for testing by the test pattern insertion circuit 14, HWO00-HWO0n, HWO1n of the outgoing highway,
And three different highways to be tested among the HWO20 to HWO2n, and the data comparison circuit (0) 12
The data comparison circuit (n) 13 selects two of the three output data, compares the data, compares the data in all three combinations, and determines whether there is a failure based on the comparison result. Judgment was made and the location of the failure was identified. FIG. 8 shows a data comparison circuit in a conventional test system. The presence or absence of a failure can be determined from the values of the outputs A, B, and C of the data comparison circuit (m) 15, and the location of the failure can be specified. For example, if the values of A, B, and C are all “0”, 3
Since the output data of the books match, it can be determined that there is no failure. If the value of A is "1", the value of B is "1", and the value of C is "0", the output data of the time switch (0) 9 and the time switch (1) 10 are unmatched,
The output data of the time switch (0) 9 and the time switch (2) 11 are also unmatched, and the output data of the time switch (1) 10 and the time switch (2) 11 match, so there is a failure somewhere. The fault location can be specified to be the time switch (0) 9. Similarly, if the time switch (1) 10 fails, the time switch (2)
Even when 11 is a fault, the fault location can be specified by the values of A, B, and C, respectively. However, assuming now that the same location has failed in both the time switch (0) 9 and the time switch (1) 10, the values of A, B, and C are all "1", and It is only possible to know that there is a disability, but it is not possible to specify which part is the disability. That is, when the same part has failed in both the time switch (0) 9 and the time switch (2) 11, and the time switch (1) 10 and the time switch (2)
This is because the values of A, B, and C are all "1" and cannot be distinguished from each other even when the same part has failed in both of them. As described above, in the related art, when a plurality of highways have failed in the same manner, there is a disadvantage that only the presence or absence of a failure can be determined and the location of the failure cannot be specified.

[0003]

In the prior art, two or three highway data are compared, and if a plurality of highways have failed in the same way, there is a drawback that the location of the failure cannot be specified. Was. The problem to be solved by the present invention is to make it possible to specify a fault location even when a plurality of highways have failed in the same manner.

[0004]

In order to achieve the above-mentioned object, all time slots on the entrance highway of the communication channel device are provided with:
By writing the same fixed data that does not change for each frame from the test data generation circuit at the same time, reading it out to the same output highway, and comparing the read highway data with the same data sent from the test data generation circuit, multiple highways In the same way, it is possible to specify the location of the failure even if it has failed.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows the overall configuration of the continuity test of the present invention. In this embodiment, it is assumed that the communication path device is constituted by a time switch. Except during the continuity test, the input-side highways HWI00 to HWI0n are time-converted by the time switch (0) 2 and connected to the time slots of the output highways HWO00 to HWO0n. Also the entrance highway HW
I10 to HWI1n are time-converted by the time switch (1) 3 and connected to the time slots of the output highways HWO10 to HWO1n. The time switch (0) 2 and the time switch (1) 3 are each a separate highway time switch. Is composed. In this embodiment, the highway of the time switch has a serial speed of 32 MHz. When the continuity test state is notified by the TST signal, the test pattern created by the pattern data generating circuit 1 is simultaneously inserted into all the time slots on the input highway of the time switch by the test pattern inserting circuit 6, and Sends the same data to two time switches. As shown in FIG.
It can be easily configured by taking an exclusive OR of the M clock and the pattern selection signal. This test pattern is "55" when the pattern selection signal is "0" as shown in FIG.
If the pattern selection signal is set to "1", a pattern which repeats "AA" is transmitted, and any pattern can be selected by the pattern selection signal. If the pattern selection signal is fixed to either “0” or “1”, the same fixed pattern that does not change for each frame is created. The time switch is controlled by the time switch (0) 2 and the time switch (1) 3 in the same manner.
The test pattern is connected to the same time slot on the same highway by the time switch (0) 2 and the time switch (1) 3. As a result, the data output from the two time switches has the same test pattern and the same time conversion, so that the same data is output to all the time slots. FIG. 4 shows the data comparison circuit (m) 7 in the output highway m. As the output data of the time switch, the same data is output to all the time slots, and the data comparison circuit (m) 7
Since the test pattern transmitted to all the time slots is the same data, the data comparison circuit (m) 7 does not need a phase synchronization or time slot extraction function, and outputs the output of the two time switches to generate pattern data. It is sufficient to simply compare the test pattern sent from the circuit 1 with all the time slots, and it is possible to use a circuit in which the output highway of each time switch and the test pattern are simply compared by exclusive OR. When the result of the comparison is notified by the TST signal that the state is the continuity test state, the gate is opened, and the result of the comparison can be read from a higher order. As shown in FIG. 4, it is possible to easily identify a fault location by the values of the outputs A and B of the data comparison circuit (m) 7. For example, if the values of A and B are both "0", it is determined that there is no fault because the two output data of the time switch (0) 2 and the time switch (1) 3 respectively match the test pattern. it can. When the value of A is “1” and the value of B is “0”, the comparison result between the output data of the time switch (0) 2 and the test pattern is unmatched, and the time switch (1) 3
Since the output data and the comparison result of the test pattern coincide with each other, it can be specified that the fault location is the time switch (0) 2. Similarly, the value of A is "0" and the value of B is "1".
In this case, the output data of the time switch (0) 2 and the comparison result of the test pattern match, and the output data of the time switch (1) 3 and the comparison result of the test pattern are unmatched. 1) It can be specified that 3 is a failure. If the values of A and B are both "1", since the output data of the time switch (0) 2 and the output data of the time switch (1) 3 are both unmatched with the test pattern, the time switch (0) 2, It can be specified that both the time switches (1) 3 are faulty. Next, specific examples of unmatch detection are shown in FIGS. FIG. 5 shows that bit 1 of time slot 0 of time switch (1) 3
Is a mismatch output on the m highway when data that should be "1" becomes "0" due to a time switch memory failure, and bit 1 of time slot 0
Since the data of O1m is "0" and the data of the test pattern is "1", the exclusive OR of HWO1m and the test pattern becomes "1", and the time switch (1) 3 becomes an obstacle. Can be identified. Also, at this time, bit 1 of time slot 0, the data of HWO0m is "1" and the data of the test pattern is "1", so that the exclusive OR of HWO0m and the test pattern becomes "0". It can be seen that the time switch (0) 2 is normal because the matching has been achieved. Next, FIG.
Is an example of unmatch detection on the m highway when a plurality of time switches have similarly failed. In this figure, a time switch memory failure occurs in the same manner at bit 1 of time slot 0 of time switch (0) 2 and time switch (1) 3, and data that should be “1” becomes “0”. The HWO0m data is “0”, the HWO1m data is “0”, and the test pattern data is “1” at bit 1 of time slot 0, so that HWO0m and the test pattern are exclusive. When the logical sum is obtained, it becomes "1", and it can be specified that the time switch (0) 2 has become an obstacle. At this time, since the exclusive OR of HWO1m and the test pattern is also "1", it can be specified that the time switch (1) 3 has also failed. In this way, with this method, all highways and all time slots can be tested in a lump, so the path setting of the time switch only needs to be set first, and the path is set individually for each highway and each time slot for testing. Processing such as inserting a pattern and checking continuity is unnecessary. The reading of the unmatched data is started from the time when the path setting of the first time switch is completely completed and the data delay time of the time switch is added, and monitoring is performed for at least one frame. During this time, unmatch occurs even once. In this case, it may be determined that a failure has occurred. If this is performed for both the “55” pattern and the “AA” pattern, the confirmation is performed by changing “0” and “1” for all bits. Therefore, the time required for the continuity test is the time for setting all the paths of the time switch, the data delay time of the time switch,
In addition, the continuity test can be completed in a very short time by only setting time for selecting a test pattern to be used. Further, at this time, even if a plurality of highways have failed in the same manner, it is possible to specify the location of the failure. Further, in the configuration of the present invention, whether the input / output of the time switch is serial or parallel, the comparison on the output highway has no effect because it is performed in bit units. In this embodiment, the highways of the different time switches are used, but it is obvious that the highway of the same time switch is also effective. An example of another implementation method of the continuity test configuration described above will be described below. The first is to constantly monitor the normality of conduction even during a non-conductivity test. This is because the test pattern inserted in all time slots during the continuity test is set so that the test pattern insertion circuit inserts the pattern data only into a specific time slot during the non-continuity test. May be set so that the path of the time switch is connected to a fixed position, and the data comparison circuit compares only the time slots connected to the fixed position. As a result, the normality of conduction can be constantly monitored even in a normal operation state. The second relates to a continuity test in a system in which time switches are connected in multiple stages. In the embodiment, the time switch has a one-stage configuration. However, the time switch does not necessarily have to have a single-stage configuration. Even in a system in which a plurality of time switches are connected, each time switch performs the same control as that of the embodiment, and outputs. By comparing the data with the test pattern, it is possible to conduct a continuity test of the entire system in a short time and to specify a fault location. The third concerns test patterns. In the embodiment, “55” pattern and “A”
Although the A "pattern has been described, the test pattern is not limited to this pattern, and other test patterns can be used. This is because a pattern data generation circuit stores a plurality of types of test patterns in a memory or the like. This can be realized by providing a function of generating a pattern and selecting and using a test pattern to be used by a pattern selection signal.The fourth relates to comparison of test patterns.In the embodiment, a test pattern is generated by a test pattern generation circuit. Is sent to the data comparison circuit from
It is not always necessary to adopt such a configuration. Since the same pattern is originally sent to all time slots,
A memory may be provided in the comparison circuit, and the same pattern as the test pattern to be used may be stored in advance. By comparing the pattern read from the memory with the highway data, a continuity test can be performed in the same manner to identify a faulty part. At this time, the pattern generation circuit and the data comparison circuit may be integrated, and the memory used for each circuit may be shared to be one. in this case,
The test pattern read from the memory is inserted into the input highway of the time switch by the test pattern insertion circuit, and at the same time, the test pattern is compared with the data on the output highway of the time switch. In this embodiment, the time switch is used as an example of the communication path device. However, the communication path device is not limited to this.

[0006]

According to the present invention, by simply comparing the output highway of the communication device and the test pattern, it is possible to confirm the normality of the communication device and to specify a fault location, which is effective in shortening the continuity test time. Further, even when the same part of a plurality of communication path devices breaks down, the failure part can be specified, so that the failure part can be easily identified.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a pattern data generation circuit.

FIG. 3 is an explanatory diagram of pattern data contents.

FIG. 4 is an explanatory diagram of a data comparison circuit.

FIG. 5 is an explanatory diagram of a data comparison example.

FIG. 6 is an explanatory diagram of a data comparison example.

FIG. 7 is a block diagram of a conventional continuity test system.

FIG. 8 is an explanatory diagram of a data comparison circuit in a conventional test method.

[Explanation of symbols]

 1 ... Pattern data generation circuit, 2 ... Time switch (0), 3 ... Time switch (1), 4 ... Data comparison circuit (0), 5 ... Data comparison circuit (n), 6 ... Test pattern insertion circuit.

Claims (5)

[Claims] 1. A comparison circuit for comparing a test data insertion circuit and a test data generation circuit for generating test data on an incoming highway of a communication channel device, and comparing highway data with test data generated by the test data generation circuit on an output highway. A circuit, and a means for notifying the test data insertion circuit and the comparison circuit of a continuity test state, wherein the test data generation circuit generates the same fixed data that does not change for each frame as test data, The test data is simultaneously sent to the test data insertion circuit and the comparison circuit, and when the continuity test state is notified, the test data insertion circuit simultaneously inserts the test data into all the time slots of the incoming highway, The communication path device controls the test data to be transmitted on the same outgoing highway, and controls the entire time of the outgoing highway. Continuity test method, characterized in that to test the continuity of the channel device and Tsu City of the test data generated by the data and the test data generation circuit by performing a comparison of all the time slots in the comparison circuit. 2. A continuity test system according to claim 1, wherein a plurality of stages of communication path devices are interposed between said test data insertion circuit, said test data generation circuit and said comparison circuit to perform the same continuity test. 3. A continuity test system according to claim 1, wherein said test data is inserted only in said specific time slot during a non-test, and said continuity test is performed by comparing only said specific time slot in a comparison circuit. . 4. A continuity test system according to claim 1, wherein said test data generation circuit is provided with means for selecting a plurality of types of test data, and selects the test data to be used and performs the same continuity test. 5. The comparison circuit according to claim 1, wherein means for preliminarily storing the same test data as the test data generated by the test data generation circuit is provided in the comparison circuit. A continuity test method in which the same test is performed by comparing the read test data and the read data of the output highway by the comparison circuit.