JPH0685885A - Communication equipment having redundant circuit - Google Patents

Abstract

PURPOSE:To prevent transmission stop due to a fault of a line driver by comparing an input signal of plural line drivers with an output signal from them at a correct comparison timing, discriminating a fault to select fault-free line drivers and connecting them to a line. CONSTITUTION:Each line driver 3 receives an output signal being a converted serial bit string from a communication control section 20 receiving an input signal and converts the signal into a signal specified on a line and outputs the signal. Each comparator means 5 compares the input signal with the output signal of each driver 3 by using a correct comparison timing generated from a timing clock source 6. The means 5 discriminates either of a fault or a normal state depending on whether or not the input signal and the output signal of each driver 3 are equal to each other. A changeover connection means 8 selects a normal driver 3 depending on the discrimination and connects the driver to the line. Thus, a fault of a driver 3 is detected in real time to prevent transmission stop due to the fault.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a communication line connected to
Redundant switch that can switch to a non-faulty line driver, especially for communication control of computers and terminal devices that send and receive data to and from each other, especially with multiple line drivers and means for detecting faults in each line driver The present invention relates to a communication device having a circuit.

Recently, point of sale information management (Point Of Sale
s: POS system, etc., one master station (master machine) and multiple slave stations (slave machines) are connected to one or two pairs of lines, and communication is also performed by using a baseband signal and a polling response method. Is being done,
The probability of failure of the line driver of the communication control unit of each device is high, and not only communication stops but also the entire system may stop by affecting all other communication signals. A method to do is desired.

[0003]

2. Description of the Related Art FIGS. 7 (a) and 7 (b) are block diagrams of a communication system including communication devices to which the present invention is applied.

FIG. 7A shows a 2-wire communication system configuration.
A line driver 3A and a receiver 4A are provided in the communication control unit 10 of the computer 1 (that is, the master machine), and each terminal device 2
a, 2b, ─ (that is, slave unit) communication control unit 20a, 20b, ─
Are provided with line drivers 3a and 3b, and receivers 4a and 4b, to access the line in a half-duplex procedure.

FIG. 7B shows a 4-wire communication system configuration, in which the line driver 3 is connected to the communication control unit 10a of the computer 1a.
A'and receiver 4A 'are provided, and each terminal device 2a', 2b
The line driver 3a ', the communication control unit 20a', 20b ',
3b ',-and receivers 4a', 4b ',-are provided to enable full-duplex communication.

In both of the systems shown in FIGS. 7 (a) and 7 (b), the transmission signal is transmitted on a line to a predetermined physical specification (voltage, voltage,
Line driver 3A, 3a, 3b, which converts to impedance etc.)
─, 3A ′, 3a ′, 3b ′, ─ are required. These line drivers 3A, 3a, 3b, ─, 3A ′, 3a ′, 3b ′, ─ are either directly connected to the line or simple surges (changes in current, voltage and power due to external factors) It is connected to the line by adding a circuit.

[0007]

According to the above-mentioned conventional method, since the output of the line driver is connected to the outside of the device, the influence of malfunction or destruction due to external noise, static electricity, electric shock such as lightning strike, etc. The probability of receiving is extremely high.

As a result of this failure or malfunction, the output of the line driver does not affect other communication signals on the line (the output stage fails so as to have a high impedance).
In that case, damage can be done only to that device, but on the other hand, if it fails to keep giving a certain level (mark or space), it will affect all other communication signals and all devices will be unable to communicate and the whole system will be lost. There is a risk of stopping.

Further, in order to recover such a failure, it is necessary to check each device even when trying to identify a failure location, and it takes a long time to recover. There is a problem.

According to the present invention, even if a line driver fails, it can be used by switching to a line driver that has not failed. Therefore, it is not necessary to stop communication, and even if all line drivers fail, It is an object of the present invention to provide a communication device having a redundant circuit that does not affect other communication and can constantly monitor a failure of a line driver that is not connected.

[0011]

FIG. 1 shows the principle of the present invention. In the figure, 3 is a plurality of line drivers which are connected to a communication control unit 20 for converting a signal to be transmitted into a serial bit string, and which convert a signal transmitted / received through a line into a signal of a physical standard defined in the line, 5 is a plurality of line drivers 3
A plurality of comparing means, each of which corresponds to the above, and compares the input signal and the output signal of the line driver 3 to determine whether they are equal, 6
Is a timing clock source for giving the correct comparison timing to the comparing means 5, and 8 switches the plurality of line drivers 3 in accordance with the judgment outputs of the plurality of comparing means 5 to connect the output of any one of the line drivers 3 to the line. It is a switching connection means.

Therefore, the switching connection means 8 is configured to switch and connect the plurality of line drivers 3 in accordance with the outputs of the plurality of comparison means 5.

[0013]

The method of detecting the failure of the line driver 3 can be confirmed by checking that the input signal and the output signal of the line driver 3 are simultaneously changing. However, since there is a signal propagation delay inside the line driver 3, the comparison means 5 cannot simply compare. In general, when performing communication by the multi-drop method, since a synchronous communication method is adopted, the output of the comparison means 5 is sampled at this transmission clock and at the center of the change point of the data for each 1-bit transmission data. Just compare.

However, since this comparison must not be performed by the transmission signal of another device, this clock is controlled so that it is generated only during the transmission of its own device. That is, while the correct comparison timing is given from the timing clock source 6, the input signals and output signals of the plurality of line drivers 3 are compared by the plurality of comparing means 5, and the output of this comparing means 5 is
If “match”, the line driver 3 is normal, and if “mismatch”, the line driver 3 is out of order.

Therefore, depending on the judgment output of each of the plurality of comparing means 3, that is, if the judgment output of any of the comparing means 5 is "match", one of them is appropriately selected by the switching connecting means 8. To connect the line driver 3 to the line.

If the judgment output of any one of the comparing means 5 is "mismatch", the switch connecting means 8 makes "match".
The line driver 3 on the output side is connected to the line. If all the judgment outputs of the plurality of comparing means 5 are "mismatch", all the line drivers 3 are out of order. Therefore, the switching connecting means 8 selects an appropriate line driver 3 and disconnects the connection. To do.

In this way, since it is possible to select the line driver 3 which has not failed in the plurality of line drivers 3 and connect the lines, it is possible to prevent the communication from being stopped due to the failure of the line driver 3. .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to the computer and each terminal device described in the conventional example will be described below with reference to FIGS. Computers 1 and 1a of FIGS. 7 (a) and 7 (b)
Since the present invention can be similarly applied to the terminal devices 2a, 2b,-, 2a ', 2b',-, the terminal device 2a will be described below as an example.

FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is an explanatory diagram showing comparison timing of the embodiment, FIG. 4 is an operation explanatory diagram of the connection selection unit, FIG. 5 is an operation explanatory unit of the switching control unit of the embodiment, and FIG. 6 is a flowchart of the embodiment. The same reference numerals denote the same objects throughout the drawings.

FIG. 2 illustrates the communication processing unit of the terminal device 2a. In the figure, 3a and 30a are line drivers, 4a and 40a are receivers, and 5a and 5b are flip-flops (hereinafter referred to as FF).
A circuit, 6a is a clock generation unit, 7 is a connection selection unit, 8a is a switching unit, 9 is a connection unit, 11 is a test pattern generation unit, 12 is a switching control unit, 13 and 14 are EXOR (exclusive OR) circuits, 15,1
6 is an AND (logical product) circuit, 20A is a communication control unit, 17 is an information processing unit, and 18 is a communication processing unit.

According to the present invention, a plurality of line drivers 3a and 30a are provided, the input signal and the output signal of the line drivers 3a and 30a are compared with each other to check whether or not there is a failure, and select the one without a failure to connect the line. Therefore, the line driver 30a, the receiver
40a, EXOR circuit 14, AND circuit 16, and FF circuit 5b
Is a backup system (redundant circuit).

The line drivers 3a and 3b and the FF circuits 5a and 5 shown in FIG.
b and the clock generator 6a correspond to the line driver 3 and the timing clock source 6 of FIG. 1, respectively.
The circuits 13 and 14, the AND circuits 15 and 16 and the FF circuits 5a and 5b are
Corresponding to the comparison circuit 5 of FIG. 1, the connection selector 7 of FIG.
The switching unit 8a and the connecting unit 9 correspond to the switching connecting unit 7 of FIG.

The information processing section 17 edits the transmission data into a transmission message and the reception message into a reception data. The communication processing unit 18 controls transmission / reception of transmission / reception telegrams. Communication control unit
The 20A performs parallel / serial conversion on the data to be transmitted (TXD), converts the received data (RXD) to serial / parallel, and at the same time transmits a transmission request signal (RTS). It also includes a clock generator 6a. The clock generator 6a generates a transmission timing clock signal (TXCLK) that supplies the FF circuits 5a and 5b with correct comparison timings of the input signals and output signals of the circuit drivers 3a and 30a.

The line drivers 3a and 30a are a plurality of line drivers which are switched to each other and used for data transmission when a failure occurs as described later. The receivers 4a and 40a receive the data and the outputs of the line drivers 3a and 30a sampled for the failure check of the line drivers 3a and 30a at the time of transmission.

The FF circuits 5a and 5b are, for example, TTL (SN7474 manufactured by Texas Instruments (TI), USA).
Equivalent), EXOR circuits 13 and 14 and an AND circuit
The line driver 3 outputs "1" when the logic levels of the two inputs from 15 and 16 are different.
When the input signal and output signal of a and 30a are different (failure), "1" is output respectively. However, since this comparison must not be made with the transmission signals of other devices, the FF circuit 5
The clocks (CK) of a and 5b are controlled so that they are generated only during transmission of the own device.

As shown in the time chart of FIG. 3, the signal received through the line drivers 3a and 30a has a propagation delay, and since there is a deviation from the transmission data, the comparison timing is set so as not to have this influence. , EX with this transmission clock
The outputs of the OR circuits 13 and 14 are sampled, and the outputs of the EXOR circuits 13 and 14 are compared at the center of the change point of data for each 1 bit.

As shown in FIGS. 4 (a) and 4 (b), the connection selecting section 7 transmits the control operation signals X and Y according to the output signals A and B from both the FF circuits 5a and 5b. Select the one that has not failed, and give an instruction to the switching unit 8a and the connecting unit 9,
8a is switched to either side of the line drivers 3a, 30a which have not failed, and the connection section 9 is connected to the line. That is, the combination of the output signals A and B

In [00] or [01], the control operation signal X connects the signal D1 and the control operation signal Y connects the line. In [10], the control operation signal X connects the signal D2 and the control operation signal Y connects the line. In [11], the control operation signal X connects the signal D2 and the control operation signal Y does not connect the line.

The switching unit 8a switches to the one in which the line drivers 3a and 30a are not in failure, based on the selection of the connection selection unit 7. The connection unit 9 is the line driver 3 switched by the switching unit 8a.
Connect either a or 30a to the line.

The test pattern generator 11 is a circuit driver.
The check signal and the clock signal for supplying the correct comparison timing of the input signal and the output signal of 30a to the FF circuit 5b are generated. This is provided to constantly check whether or not the line driver 30a is normal when the line driver 3a is used during communication.

The switching control unit 12 includes a clock signal A1 and transmission data A2 from the communication control unit 20A, a clock signal B1 generated by the test pattern generation unit 11 and a check data.
Controls switching of connection with B2. That is, as shown in FIG.
As shown in (b), line driver 3a and line driver 30
When checking the failure of a, and the line driver 30a
Is connected to the line (the line driver 3a is faulty and is being transmitted by the line driver 30a), the output C1,
C2 and C3 respectively output a clock signal A1, transmission data A2, and a signal A3 that enables transmission of the line driver 30a, and the line driver 30a is not connected to the line (line driver 3a
The output C1 and C2 output the clock signal B1 and the transmission data B2, respectively, and the output C3 is controlled to always output "1".

Having such a structure and function, the operation will be described below with reference to the flowchart of FIG. The transmission data edited by the information processing unit 17 and sent to the communication processing unit 18 is formed into a frame by the communication control unit 20A according to the protocol on the line, converted into serial data, and output from the TXD terminal. Line driver at the same time
The RTS terminal that enables transmission of 3a and 30a is turned on, and serial data is input to the line drivers 3a and 30a. At this time,
The transmission signal is converted into a signal voltage on the circuit through the receivers 4a and 4b, and is input to the EXOR circuits 13 and 14 together with the inputs of the line drivers 3a and 30a so that the signals can be transmitted.

The EXOR circuits 13 and 14 output "1" when the two signals are different. However, since this output is not exactly the same in time due to the delay of the circuit parts, the FF circuit 5
Added to a, 5b inputs. The clock signal to the FF circuits 5a and 5b is obtained by ANDing the transmission clock of the communication control unit 20A and the signal of the RTS terminal in the AND circuits 15 and 16, and the clock signal is ANDed only when the transmission data is valid. Output from circuits 15 and 16. This FF circuit 5a, 5b makes E
The outputs of the XOR circuits 13 and 14 are sampled at the center of the change point of the transmission signal, so that they have a sufficient margin and the problems such as the delay of the above circuit parts are eliminated. Where this F
The fact that the outputs A and B of the F circuits 5a and 5b become "1" means that the inputs of the EXOR circuits 13 and 14 are different, that is,
It can be determined that the line drivers 3a and 30a are out of order. (Receivers 4a and 4b may also fail, but line driver
Since the failure rate of 3a, 30a is higher, the possibility of failure of the receivers 4a, 4b is less. ) If the outputs A and B of the FF circuits 5a and 5b are

If it is [00] or [01], the connection control unit 7 instructs the switching unit 8a by the control operation signal X to connect the signal D1, and the control operation signal Y
Then, the connection section 9 is instructed to connect the line. That is, when the driver circuit 3a has not failed, the driver circuit 3a is selected and connected.

If the outputs A and B are [10], the switching unit 8a is instructed by the signal X to connect the signal D2, and the connecting unit 9 is instructed by the signal Y to connect the line. That is, when the driver circuit 3a has failed but the driver circuit 30a has not failed, the driver circuit 30a is selected and connected.

If the outputs A and B are [11],
Since both of the line drivers 3a and 30a are out of order, the switching unit 8a is instructed by the signal X to connect the signal D1, and the connection unit 9 is instructed by the signal Y to disconnect the line.

When the line driver 3a is selected as described above and transmission of transmission data to the computer 1 (not shown) is started, the switching controller 12 tests the outputs C1 and C2 from the clock signal A1 and the transmission data from the signal A2. Clock signal B1 and test data sent from the pattern generator 11
Switch the connection to B2.

Thus, the line driver 30a uses the clock signal
Whether or not there is a failure is constantly checked by B1, the test data B2, and the signal A3 that enables transmission of the line driver 30a, and the output of the FF circuit 5b is sent to the connection selection unit 7.

If a failure occurs in the line driver 30a, recovery action is taken without stopping the transmission by the line driver 3a. After starting transmission by the line driver 3a above,
When a failure occurs in the line driver 3a, the flow is immediately switched to the line driver 30a (that is, the signal D2).

In this way, a plurality of sets of line drivers 3
a, 30a, receivers 4a, 40a, FF circuits 5a, 5b, EXOR circuits 13, 14 and AND circuits 15, 16 are provided as redundant circuits, so that the input and output of the line drivers 3a, 30a are compared and a failure occurs. It is possible to prevent the transmission from being stopped due to a failure of the line driver because it is possible to connect the line by determining whether there is any error and switching to the one that has not failed.

Further, by providing the test pattern generating section 11 and the switching control section 12, it is possible to constantly check the failure of the line driver 30a after the transmission of the line driver 3a is started, the diagnosis rate of the failure is improved, and the transmission is improved. The repair process can be performed without stopping, and when the line driver 3a fails, the line driver 30a can be immediately switched to.

In the above example, the case where claim 1 is included in claim 2 has been described, but even if only claim 1 is implemented, the line driver 30a cannot always be checked.
It is possible to judge whether there is a failure by comparing the inputs and outputs of 3a and 30a, switch to the one that does not have a failure and connect the line, and prevent the transmission from being stopped due to the failure of the line driver. Is obtained.

[0041]

As described above, according to the present invention,
According to claim 1, a plurality of line drivers 3 connected to a communication control unit for converting a signal to be transmitted into a serial bit string and converting a signal transmitted / received via the line into a signal of a physical standard defined by the line. A plurality of comparing means corresponding to the plurality of line drivers respectively, comparing the input signal and the output signal of the line driver to determine whether they are equal, and a timing clock source for giving a correct comparison timing to the comparing means,
A line driver failure detection is performed at the time of operation by providing a switching connection unit that switches a plurality of line drivers according to outputs of a plurality of comparison units and connects the output of any one of the line drivers to a line. The failure can be detected in real time, and when there is a failure, the line can be switched by switching to the one that has not failed, so it is possible to prevent transmission stoppage due to a failure of the line driver. In case of failure, it can be separated so as not to affect other communication.

According to a second aspect of the present invention, a test pattern generating means for generating a test signal and a comparison timing signal is provided, and a test generated by the test pattern generating means is applied to a line driver which is not connected to a line among a plurality of line drivers. By inputting the signal and the comparison timing signal and comparing the input signal and the output signal of the line driver by the comparison means, it is possible to constantly check the occurrence of the line driver fault not connected to the line, so that it is possible to diagnose the fault. The rate is improved, repair processing can be performed without stopping transmission, and switching can be performed immediately when a failure occurs in the line driver connected to the line. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a comparison timing of the embodiment.

FIG. 4 is an operation explanatory diagram of a connection selection unit according to the embodiment.

FIG. 5 is an operation explanatory diagram of the switching control unit according to the embodiment.

FIG. 6 is a flowchart of an embodiment.

FIG. 7 is a block diagram showing a communication system to which the present invention is applied.

[Explanation of symbols]

1,1a is a computer, 2a, 2b, 2a ', 2b' is a terminal device, 3,3A, 3A ', 3a, 30a is a line driver, 4A, 4A', 4a,
4b, 4a ', 4b' are receivers, 5 is comparison means,
5a and 5b are FF circuits, 6 is a timing clock source,
6a is a clock generator, 7 is a connection selector, 8
Is a switching connecting means, 8a is a switching unit, 9 is a connecting unit, 10, 20, 20a, 20b, 20a ', 20b', 20A are communication control units, 11 is a test pattern generating unit,
12 is a switching control unit, 13 and 14 are EXOR circuits, 15 and 1
6 is an AND circuit,

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Fushi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. A plurality of units connected to a communication control unit (20) for converting a signal to be transmitted into a serial bit string and converting a signal to be transmitted via a line into a signal of a physical standard defined by the line. Line driver (3) and a plurality of comparing means (5) corresponding to the plurality of line drivers (3) respectively and comparing the input signal and the output signal of the line driver (3) to determine whether they are equal or not A timing clock source (6) for giving a correct comparison timing to the comparing means (5), and switching between the plurality of line drivers (3) in accordance with the judgment outputs of the plurality of comparing means (5). A communication device having a redundant circuit, comprising: switching connection means (8) for connecting the output of one line driver (3) to a line. 2. A test pattern generating means for generating a test signal and a comparison timing signal, the test pattern generating means for a line driver (3) not connected to a line among the plurality of line drivers (3). 2. A communication device having a redundant circuit according to claim 1, wherein the test signal and the comparison timing signal generated from the circuit are input, and the input signal and the output signal of the line driver (3) are compared by the comparison means (5). .