SU1410047A1 - Switching system - Google Patents

Abstract

This invention relates to the field of computing. The goal is to accelerate the recovery of performance in case of information bus failure. The switching system contains switches 1 interconnected with subscribers and information buses, exchange control devices interconnected by a polling line, and with switches control lines. The essence of the invention consists in the introduction of recovery units and control units included in the break of information buses between switches, at their beginning and at the end and connected to devices for exchanging fault indication lines. 2 f-ly, 5 silt, 1 tab.

Description

four;

ten

11410047

The invention relates to computing and can be used in the construction of information exchange systems between computers or between modules of multiprocessor computer complexes.

The aim of the invention is to accelerate system recovery in the event of a bus failure.

Fig. 1 shows the block diagram of the switching system, Fig. 2-75, respectively, of the selector circuit, the control unit, the switch and the exchange control device.

The switching system (Fig. 1) contains M switches 1 connected to each other and to N subscribers 2 information buses 3. The exchange control devices 4 are connected to switches 1 by control lines 5, the number P of which is equal to the number of information buses. The polling line 6 sequentially passes through all the exchange control devices 4 and forms a 25 ring, in the gap of which the initial start circuit 7 is included. Each address bus 8 connects the subscriber 2 to the corresponding exchange control device 4. At the switch output, the information busbar 3 is turned on by recovery blocks 9, and at the switch 1 output, control unit 10 is also included in the information bus 3. Each pair of blocks 9 and 10 adjacent to the switch 1, connected to the parallel information buses 3, is interconnected by a bus 11 of the loop. The control blocks 10 are connected with the devices 4 controlling the exchange of the fault indication lines 12

The assignment of devices and communications is as follows. The switches 1, by signals on the control lines 5, provide for the connection of information buses 3, the sequence of which included in the route allows subscribers 2 to exchange data. The device 4 control the exchange in accordance with the address set on the address

thirty

35

40

45

When a failure is detected, together with block 9, it reappears when a device 4 is impacted by a pulse cycling in the polling line 6. A start-up circuit 7, containing a one-shot connected to the input of the OR element, which is included in the discontinuity of the interrogation line 6, allows this pulse to be formed when the switching system is turned on. Each control unit 10 is designed to detect a failure in the area between blocks 10 and 9 of one of the information bus lines.

the process of determining the number of the failed line and the subsequent switching on of the reserve line instead of it, which is part of the information bus 3; Bus 11 is used for transmission already; a certain number of the failed line to the parallel information bus 3 and further to recovery block 9 for switching on the backup line. In addition, the control units 10 by issuing signals on the fault indication line 12 provide for blocking the use of the failed (and parallel) information bus for recovery time in the event of a single data line in bus 3 and prohibiting the use of such bus 3 in the event of two or more failures lines.

The recovery unit (Fig. 1) contains a group of 13 elements of the SHS multiplexer 14, a register 15, a driver of 16 pulses. A backup line 17 is connected to the output of the multiplexer 14; part of the information bus 3, Blocks U and 9 are connected by a line 18. Recovery management, which in block 9 is connected to the input of the imaging unit 16 and to one of the inputs of each element of the group 13 of the OR elements.

The assignment of nodes and connections is as follows. A group of 13 OR elements, each of which has three inputs, ensures the transfer of information between switches 1 via the information bus Z

bus 8 subscriber initiator 2, in the mode of normal operation, and in mode

0

five

0 5

0

five

0

five

When a failure is detected, together with block 9, it reappears when a device 4 is impacted by a pulse cycling in the polling line 6. A start-up circuit 7, containing a one-shot connected to the input of the OR element, which is included in the discontinuity of the interrogation line 6, allows this pulse to be formed when the switching system is turned on. Each control unit 10 is designed to detect a failure in the area between blocks 10 and 9 of one of the information bus lines.

the process of determining the number of the failed line and the subsequent switching on of the reserve line instead of it, which is part of the information bus 3; Bus 11 is used for transmission already; a certain number of the failed line to the parallel information bus 3 and further to recovery block 9 for switching on the backup line. In addition, the control units 10 by issuing signals on the fault indication line 12 provide for blocking the use of the failed (and parallel) information bus for recovery time in the event of a single data line in bus 3 and prohibiting the use of such bus 3 in the event of two or more failures lines.

The recovery unit (Fig. 1) contains a group of 13 elements of the SHS multiplexer 14, a register 15, a driver of 16 pulses. A backup line 17 is connected to the output of the multiplexer 14; part of the information bus 3, Blocks U and 9 are connected by a line 18. Recovery management, which in block 9 is connected to the input of the imaging unit 16 and to one of the inputs of each element of the group 13 of the OR elements.

The assignment of nodes and connections is as follows. A group of 13 OR elements, each of which has three inputs, ensures the transfer of information between switches 1 via the information bus Z

 in normal mode and in normal mode

They excite the excitation of certain lines 5 of the control to route the route to the addressee. Capturing the route is possible only after installing on certain signal control lines 5 1, eliminating conflicts between different control resolution exchange control devices 4 — entering test effects from recovery control line 18. In addition, the parallel bus line — 3 () —through a group of 13 elements OR — from the bus 11 (11) of the loop, the code of the number of the failed line goes to bus 3. Multiplexer 14 connects

backup line 17 instead of the failed line in the data bus. It contains two-input elements AND, combined with the element OR. The inputs of each element I are connected to one line of the information bus 3 and to the output of the corresponding trigger register 15. In this register, at the end of the recovery process, the position code of the number of the failed line is entered, which is fed through the parallel information bus. Code entry is made on the synchronization signal at the output of the imaging unit 16, which highlights the leading edge of the signal on the recovery control line 18. Shaper 16 delays an extra signal for the time allowed for recovery.

The control unit 10 (Fig. 1) contains a selector 19, a distributor 20, a register 21, a control unit 22, a group of 23 elements I. A failure localization 24 is included in the information bus 3 and is connected to the output of the control node.

The assignment of nodes and connections is as follows. The selector 19 allows you to receive information from the backup line 17 and transfer it towards switch 1 to that information bus line 3, the number of which coincides with the number that failed in the area between blocks 9 and 10 of the line. Register 21 is designed to store the number of the failed line and control the selector 19. It has synchronizable inputs of installation 1 to which an information bus is connected, a synchronization input and asynchronous counting inputs to which the first and second outputs of the distributor 20 are connected, the third output of which is connected to knzsh; the input of a group of 23 elements I. The listed inputs of register 21 provide for receiving from the bus 3 results of test actions and forming the number of the failed line as follows.

It is assumed that the information bus line 3 may be a failure of type Constant zero or Constant one, with the most likely single failure. To obtain the number of the failed line in the positional code, first all bus 3 lines from block 9 are transmitted 1 and entered into the register by a synchronization signal.

21, then from distributor 20 are received 1 to the counting inputs of register 21 and, finally, from block 9 are transmitted 0 and transferred from bus 3 by synchronization signal to register 21. The table shows the state of register 21 after receiving the results of test actions (for bounce line number 2).

Act

Register bit numbers 21

15

Sill

Type Constant null failure

К For the result of the test All units 10111

2. Addition modulo

two from 1 01000

3. Record the test result All

zeros 01000

Constant type one failure

1. Recording the result All units 11111

2. Addition modulo

two with 1 00000

3. Recording the test result All

zeros

O 1 O b o

For any type of fault in the register, the position code of the failed line number is formed.

A group of 23 elements And is necessary to obtain the received number on the bus 11 of the loop by the signal at the third outlet of the distributor, formed at the end of the restoration.

The distributor 20 selects the leading edge of the signal on the recovery control line 18 and generates signals in the following sequence: at the first output, at the second output, at the first output, and at the third output. It contains an input driver connected to a circuit of three delay elements. The outputs of the former and the second delay element are connected to the inputs of the RSII element, the output of which is the first output

The cops delay form the second and third outputs of the distributor. Each delay element delays the signal by the time required for operation. 51

neither the register 21, the control unit 22, the group 13 of the OR elements, and the propagation of signals along the recovery control line 18 and over the information bus 3.

At control unit 22, it is possible to detect the fact that the information bus has failed and to issue signals to the fault indication line 12 and the fault localization line 24, as well as to generate a signal on the recovery control line 18 in case of detecting the first bus failure 3,

The selector 19 (FIG. 2) contains a group of 25 elements OR, combining pairs of elements I. The first inputs of the elements AND of each pair are connected respectively to the information bus line 3 and the backup line 17, and to the second inputs to the inverter and the output of the register trigger 21. In the zero state of register 21, the outputs of the selector 19 provide information with the bus line 3. If the k-th trigger of the register 21 stores a unit, indicating that the k-bus line 3 needs to be restored, then at the kM output of the selector 19 is information from backup oh line 17

The control unit 22 (FIG. 3) comprises an adder 26 modulo two, a trigger 27, elements OR 28 and 29, an element 30, a delay element 31, and a pulse shaper 32. The purpose of the elements and relations is alending. Modulo 26 admits detection of information bus 3 failure, for which a control line for odd-bit discharge is entered into its composition. If one of the information bus 3 lines fails — Constant one or Constant Zero — one of the combinations with an even number of units is supplied to the inputs of adder 26, so the signal from the inverse output of adder 26 triggers 27 to 1. The trigger 27 is intended to indicate a bus failure 3. Line 24 of localization of failure with elements OR 28 allows fixing the place of failure with an accuracy of one information bus 3. In the absence of line 24, failure of one bus 3 would cause installation of 1 triggers of 27 control nodes connected to buses 3, 3 in alone in the route. In this case, the subsequent control nodes would fix not the failure, but the fact of the transfer of the code distorted in the bus 3.

47 6

Connecting line 24 to the input of the installation in O of the trigger 27 and to the input of element 28 allows you to install in O of the triggers in the nodes 22 of the control connected to the buses 3, 3 .... As a result, only on line 12 of the indication of failures according to a Wits signal indicating the. bus failure 3 °. This signal will destroy the route involving bus 3.

The .32 shaper is designed to sample the signal that controls the issuance of the test All units, with a delay

the leading edge for a time sufficient to trigger the exchange control devices 4 and the switches 1 when the route is destroyed. The elements OR 29 and AND 30 allow you to establish whether the failure of the same information bus 3 was recorded previously. If the failure was not previously recorded, then there was no recovery process, therefore in register 21 all triggers will be found

in the state O, therefore, the signal from the output of the imaging unit 32 will pass through the element 30 to the recovery control line 18 and to the input of the element 31 of the delay. The restoration process will begin, as a result of which the number of the failed line will go to register 21. The trigger 27, after restoring the tire 3, will be set to O with a signal from the output of the delay element 31. With a new failure of the same bus, the signal passing through the AND 30 element will be prohibited, therefore the recovery process will not be repeated, and the trigger 27 will not be reset to O. This will indicate a fatal failure.

Switch 1 (FIG. 4) contains AND 33 elements and AND-34 elements 34 and Element 33 produces control actions on AND-34 switching elements. Control lines 5 are pairwise connected to the inputs of each AND 33 element, which are connected tires 3. The notation in FIG. 4 has such a meaning. Each line 5 is associated with a pair of parallel information buses 3, designed to transmit information between two switches 1, in contrast to

directions. For example, line s corresponds to a pair of tires: 3 and 3,, If necessary, connect two pairs. tire 3 should excite two lines 5 control, which are mapped to each

7 1

doi pare The output element And 33 controls the switching of two pairs of information buses, the numbers of the connected buses once separated by a slash. The connections of the output of each element And 33 through inverters with the inputs of other elements And 33 are necessary so that after the switch 1 establishes a connection between two pairs of buses 3 to exclude the connection of the new information buses 3 to them in the same commutator in case of excitation, the other lines 5 management

The exchange control device 4 (FIG. 5) contains an OR element 35, a group of 36 OR elements, a comparison circuit 37, a route memory 38, a comparison circuit 39, an AND 40 element, a trigger 41, a delay element 42, a group of 43 elements I.

The purpose of the blocks and communications is as follows. Route memory 38 stores route codes from a given subscriber, for example, 2 to all other subscribers. The unit at the Pth position of the kth cell means that the information busses and enter the route from subscriber 2 to subscriber 2. For example (Fig. 1), in the cell N of the route memory 38 in the exchange control device 4, the units are located at positions 1, 2, 6, i.e. Information buses 3 and 32, 33 and 3% 3 and 3 are included in the route from subscriber 2 to subscriber 2. The circulation in the memory 38 of the routes is made in accordance with the address of the destination subscriber assigned by the initiating party over the address bus 8 and held during the exchange. The OR element 35, when an address arrives, generates a signal that triggers the device 4. The comparison circuit determines the possibility of trapping, the route. It contains AND elements, the inputs of each of which are connected to the information output of the memory 38 routes and to the corresponding line 5; control, and the outputs are combined element OR NOT, the output of which is the output of circuit 39.

The possibility of capturing the route is revealed by comparing the route code with the state of the lines 5, reflecting the occupancy of the corresponding tire pairs 3. 1 at the output of the comparison circuit 39 appears if all the elements are output. And O, This condition is possible when a pair of tires 3, entering the route.

478

free (O on the corresponding line 5) or a pair of spike 3, even if it is busy, is not included in the route (O on the corresponding memory output line

38).

The trigger 41 provides for capturing the route by issuing a permitting signal to the input of a group of 43 elements I. Tem.

most, on the control line 5, the route route code is passed, which allows you to make the necessary connections in switches 1. Capture is performed when the following conditions are met: the address on the address bus 8 and the enable signal from the comparison circuit 39, the pulse on the interrogation line 6 and the absence of a ban from the comparison circuit 37 - then element 40 will work. Group 36 of elements OR pairwise connects fault indication lines 12 for each pair of parallel information lines 3. Signal at the output of element OR of the specified group 36

indicates a failure of one of the pair of tires 3.

The comparison circuit 37 prohibits the use of a route that contains a failed data bus 3,

If a failure occurs during data exchange, circuit 37 will destroy the connection. Comparison circuit 37 contains a group of two-input AND elements combined by OR elements, the inputs of each AND element are connected to the output of an OR element of group 36 and with a corresponding memory output line. 38 routes. The signal at the output of the circuit 37 is Wits, if at least one element AND coincides, which means the use of the failed bus 3 in the route. This output signal sets the trigger 41 to 0, therefore the route code will be removed from the control lines 5 and the connection will be destroyed . Attempts to capture such a route will prove futile, as long as the prohibition signal from the output of circuit 37 is in effect - element 40 will not work.

The delay element 42 is designed to delay the signal on the polling line 6 for a time sufficient to establish a connection.

The switching system is functioning

in the following way. After power on

.

set to zero registers 15

and 21, triggers 27 in all recovery blocks 9 and control and control blocks 10. This is done by sig

The initial setup file supplied to the inputs, the settings in O of all the memory elements, the 38 memories of each exchange control device 4 in Marines, contains route codes between subscribers 2, and the Starting circuit 7 generates a signal that starts to circulate along the polling line 6.

The initiator subscriber, when it is not necessary to exchange with the subscriber, issues the address of the last one via the address bus 8 to the adjacent control device 4 and exchanges it until the end of the data exchange. The address from memory 38 reads the route code, in comparison circuit 39 it is determined whether all information buses 3 that are included in the route are free, and comparison circuit 37 reveals their serviceability, i.e. A check is made on the conditions of the route capture. With the arrival of a pulse on the polling line 6, if conditions are fulfilled, it is set to 1 flip-flop 41, allowing the route code to be controlled on line 5. The excitation of certain lines 5 causes the switches 1 to connect the information buses entering the route. Subscribers perform data exchange, after which the initiating subscriber removes the address from the address bus 8. At the output of the OR element 35, O appears, setting Trigger 41 to the State O. Thus, I prohibits the issuance of a marketing code on Control Line 5. Switches 1 destroy the established connection. I In case of a failure of the information lines of the bus line 3, the control node 22 in the control unit | 10 of the control detects the failure — it is set at 1 trigger 27. It is activated. a signal on the fault indication line 12 prohibiting the use of the bus 3 for exchange, and in case it was used at the time of the failure, ensuring the destruction of the connection.

The recovery control line 18 reaches the distributor 20, the driver 16 and the group 13 of the elements OR receives a signal. At the outputs of group 13 of the elements OR, a test action appears - from 1 along all lines of bus 3. According to the signal at the first output of the distributor 20, the result of hrecTa is entered into the register 2.1. After a time sufficient to trigger the trigger register of register 21, valve 20 generates a signal at the second output.

0

five

0

five

0

five

0

five

0

five

arriving at the register inputs trigger register 21 „

At node 22 of the control, at the output of element 30, a signal O appears at the end of operation of the imaging unit 32 and O is transmitted on line 18. Group 13 of the elements OR test output, O through all the line 3, since all three inputs of each of the element of the IPI of this group O. According to the new signal on the first input of the distributor 20, the test result is entered into the register 21.

As discussed earlier, the described tests allow you to get the S register 21 position code number of the failed line in bus 3. Signals from the third output of the distributor 20 and the output of the driver 16, produced at the same time, the number from the register 21 on the bus 11 loop, through the block 9 () across. (Enters the register 15 of block 9. The multiplexer 1A is turned on in the recovery block 9 and the selector 19 in the control block 10 is connected to the bus 3 instead of the failed backup line 17. The reset process ends. Delay 31 sets the signal c in O trigger 27. The signal from the fault indication line 12 is removed. The reconstructed data bus, 3, is again allowed to use.

In case of repeated failure of the same bus 3 will be set to 1 flip-flop 27, the signaling line 12 will be issued, prohibiting the use of this bus, but the recovery will not start, because the resources are exhausted. The presence of 1 in the register 21 will prohibit the passage of the signal from the output of the imaging unit 32 through the AND 30 element to the recovery control line 18.

Claims (3)

1. A switching system containing M switches, H exchange control devices, a start-up circuit and L control blocks (L is the number of information buses between the switches), the first information input / output of the K-th switch being the K-m information input-output system (K 1, ..., H), the address input of the K-th exchange control device is the K-th address input cvicTewiii, the polling input of the first exchange control device is connected to the output of the initial startup circuit, the restart input of which is connected to the polling output of the Nth exchange control device, and the polling output of the ath exchange control device (a 1, ..., N-1) is connected to the polling input (a + 1) -th exchange control device, the I / O controls of all the exchange control devices are connected to the control inputs of all switches, characterized in that, in order to accelerate the recovery of the system when the information bus fails, L blocks are entered into it the first information output of the first switch (1, ..., L, c 1, ..., M) is connected to the information input of the second recovery block, the output / input of which is connected via the first an information bus with the first input of the failed line number (in + 1) of the recovery block and the input-output of the control block, whose information output is connected to the d th information input of the switch (d 1, ..., L, e. 1, ..., M, c # e). The output of the number of the failed line in the th control unit is connected to the second input of the number of the failed line (in +1) of the th block No, (d + 1) -th information output of the e-th switch is connected to the information input (into + 1) of the recovery block, the output-input of which is connected via the (to + 1) -th information bus to the first input of the failed number line of the second recovery block and input-output (to + 1) block of the control, whose information output is connected to (to + 1) -th information input from the th switch, output of the number of the failed line (to + 1) block of the ontrol is connected to the second input of the number of the failed line of the 10th recovery block, the outputs of the indication of the failures of all the control blocks L are connected to the fault indication inputs of all exchange control devices. 2. System pop. 1, which differs from the fact that the control unit contains a modulo two adder, a trigger, a selector, a distributor, a register, a group of AND elements, two OR elements, an AND element, a pulse shaper, and a delay element. information input / output unit under five 0 five 0 five 0 five 0 five keys to the informational inputs of the selector and the register, the outputs of which are connected to the control inputs of the selector, the inputs of the second element PlflH and the first inputs of the corresponding elements AND groups whose outputs form the output of the failed block line number, the information output of the selector is connected to the modulo input. two informational block output, the localization bit of the selector output failures is connected to the first reset input of the trigger and the first input of the first element OR, the inverse output of the modulo two is connected with . the trigger setup input, the output of the second element OR is connected to the first inverse input of the AND element, the second input of which is connected to the output of the pulse former, the output of the AND element is connected to the clock input of the distributor, to the input of the control bit of the information input-output block.a and through the delay element with the second reset input of the trigger, the output of which is connected to the input of the pulse former, the output of the block failure indication and the second input of the first OR element, the output of which is connected to the localization discharge of the failures of the output yes of the unit, the first and second outputs of the distributor are connected to the setup inputs of the register, and the third output is connected to the second inputs of the AND elements of the group. 3. The system pop, 1, differs by the fact that the block restores a group of elements OR, a multiplexer, a register and a pulse shaper, and the information input of the block and the output of the group of elements OR are connected to the information output of the multiplexer and the information output - the input of the block, the second input of the failed line number of the block is connected to the first inputs of the elements of the OR group, the first input of the failed line number is connected to the information input of the register, the recovery control of the information output of the block with one with the second input of OR group and to the input of the pulse shaper, the output of which is connected to the reset input .triggera whose output is connected to a control input of the multiplexer, the output of which is connected to the discharge line do backup information input-output unit. gjus.if L. . 2 О / в21 fib, . 0U6, y