SU1462343A1 - Selective switching system - Google Patents

Abstract

The invention relates to computing and allows for an increase in the capacity of switching systems by reducing the response time to low priority requests. The switching system contains switches 1 interconnected and with subscribers 2 information buses 3, exchange control devices 6 connected to subscribers 2 by line 4 of the exchange request and address buses 5, among themselves by the line 9 of the survey, in the gap of which the block is included 10 polling, and with switches 1 - bus 7 control. The invention consists in introducing, by the number of priorities, bus bar requests 8 connected to exchange control devices 6, which allows subscribers to connect by low-priority requests even if there are unserved high-priority requests, unless the first ones cause interference to the second, i.e. do not claim any information bus included in the routes of high priority requests. 1 hp f-ly, 5 ill. S S (L

Description

Phi1.1

The invention relates to supervisory technology and can be used in the construction of a data exchange system between computers. Or between modules of multiprocessing computer complexes.

The aim of the invention is to increase the capacity of the system; switching,

 Fig. 1 is a block diagram of the switching system; Fig. 2 is a functional diagram of an exchange control device; FIG. 3 is a functional circuit diagram of a switch; Fig 4 is a comparison circuit; Fig, 5 is a functional diagram of the switch. J- Switching system (FIG. 1) containing M1 M of switches 1, H subscribers 2, IQ information buses 3, H address I buses 4, H buses 5 exchange request, H devices 6 exchange control, bus 7 control, ( T-1) tires 8 ban,; (T-1) elements of the 9th call, polling line 10, polling block 11, Where T is the number of priorities of exchange requests that any subscriber can initiate. Each exchange control device 6 (FIG. 2) contains a route memory block 12, an item OR 13, a switch 14, a route code bus 15, a comparison circuit 1 b, a group of 17 elements; Comrade Y, Bus 18, trigger 19; element 20 delay,

: Switch 14 (fig.Z) contains; life (T-1) of the groups 21 of the elements And and T of the groups of elements And 22, Scheme 16 Comparative, FIG (4) contains Q 2-input elements And 23 and the element OR-NO 24 per Q inputs. Each switch 1 (FIG. 5) contains AND elements 25, inverters 26 and multiplexers 27,

In order to organize the exchange, the initiator subscriber sets the address code of the recipient subscriber to address bus 4 and excites one of the bus lines 5 of the exchange request in accordance with the priority of the generated request. Signal 1 on one of the lines of bus 5 of the exchange request is detected by the element OR 13, the output of which removes the prohibition of setting the state 1 of the trigger 19. At the same time, information about the priority of the request goes to switch 14, which connects the circuit 16 comparing the second inputs to one of the tires 8 prohibition, the priority of which is at the top of the priority and the incoming request

or to the control bus 7, and the output of the route memory 12 is connected to that interdiction bus 8, the priority of which corresponds to the priority of the incoming request.

The routing memory unit 12 assigned to the initiator subscriber of the exchange control device 6, having received the recipient subscriber address, sets a route code at its outputs that goes to the first inputs of the comparison circuit 16, group I of elements 17 and through switch 14 to the corresponding bus 8 prohibition. As a result, the code of the proposed route becomes available to all other devices 6 of the exchange control. In addition, through the junction elements 9, the read code arrives on all buses 8 prohibition corresponding to a lower request. priority.

The comparison circuit 16 makes comparisons of the code received from the route memory memory 12 with the information located on the interdiction information 8 or the control bus 7. If the requested route does not intersect with a single request route of higher priority, the codes of which are placed on the inhibit bus 8, the comparison circuit 16 generates a signal 1 at its output, preparing trigger 19 to be set to state 1. With the arrival of the polling pulse, trigger 19 is set to state 1, and the signal from its direct output opens a group of 17 elements AND, through which the code of the route en route arrives at the control bus 7. The excitation of the lines of the control bus 7 leads to the triggering of the switches 1 incident to the emergency lines and, as a result, the connection between the subscribers 2 and the initiator and the receiver,

In case the requested route intersects with at least one of the specified routes, the comparison circuit 16 generates a signal O at the output, preventing the trigger 19 from being set in state 1 and thereby prohibiting the initiator from capturing the route. Thus, the capture of the route with the arrival on line 10 of the polling pulse does not occur, however, the code of the proposed route remains on the prohibition bus 8, the priority of which corresponds to the priority of the query i and on all buses 8

31

prohibiting a lower priority, cht provides a prohibition of capturing a route by any lower priority requests if their routes intersect with a given one.

Disconnection by the subscriber-initiator of the request signal at the end of the exchange leads to reset of the trigger 19, removal of the route code from the control bus 7 and destruction of the established route. At the same time, the switch 14 removes the information about the route code from the corresponding bus 8 prohibition and through the elements of the 9 exits from all lower priority tires 8 prohibition. The signal on polling line 10 is delayed by delay element 20 for the time needed to capture the route, and then transmitted to the next exchange control device 6. A request that has not received service due to the route being filled with more priority requests remains in the system until the route is released, thereby prohibiting service on the intersecting routes of lower priority requests.

Formula inventions

the OR element, the output of which is connected to the trigger reset input, the address input of the exchange control device is the address input of the route memory block, the output of which is connected to the first inputs of the comparison circuit and the AND group elements, the output of the control circuit is connected to the setup input of the trigger, the output of which is connected to the second inputs of the elements AND groups whose outputs are connected to the control input-outputs of the exchange control device, whose polling input is connected to the trigger synchronization input and through a delay element The interrogation output of the exchange control device, characterized in that, in order to increase the system capacity, (T-1) barring tires and (T-1) isolation elements (T are the number of requests priorities) are entered into it, and the prohibition bus (... T-1) is connected to the nth input-output of the prohibition of each exchange control device and through the p-th element of the interchange to the (n-1) -th bus of the prohibition, the first bus of the prohibition through the first element of the interchange connected to the control bus; a switch is inserted into each exchange control device; the input of the request and input-output ION exchange control device connected to the input

Claims (2)

1. A switching system containing M switches is interconnected with each other and with H (HiM) Q information subscribers. buses, N request control devices and with the exchange control input, connected by the switch inputs, respectively, the nth control inputs to the switches via the control bus, and the interrogator whose output is connected to the optical input 40 dew of the first exchange control device, the polling output of the K-th exchange control device (K 1 ... H-1) is connected to the polling input of the (K + 1) -th exchange control device, the polling output of the N-th exchange control device is connected to the input the polling unit, the address input and the request input of the m-th exchange control device (... H) are the m-th address input and the m-th input of the system request; the first information inputs-outputs H from M switches are m-information system inputs, each control unit the control output of the exchange control device (... T-1) is the nth input-output switch, the output of the route memory is connected to the information input of the switch, the output of which is connected to the second inputs of the comparison circuit. 45 2. The system of clause -1, characterized by the fact that each switch contains the first block (t-1) of the groups of elements And the second block of T groups of elements And, and the bits of the information input of the switch are connected to the first inputs of the corresponding elements AND groups of elements AND of the first block, bits of the n-th input, each ffl-th device of the gap “..: п„ „- prohibit the switch by interchange contains a memory block of the route — 55 seconds, the OR element, the comparison circuit, the group And elements, trigger, delay element, exchange control device request input By the entrance the outputs of the corresponding elements of the nth group of the elements of the first block and the first inputs of the corresponding elements of the nth group of ele 0 five five 0 the OR element, the output of which is connected to the trigger reset input, the address input of the exchange control device is the address input of the route memory block, the output of which is connected to the first inputs of the comparison circuit and the AND group elements, the output of the control circuit is connected to the setup input of the trigger, the output of which is connected to the second inputs of the elements AND groups whose outputs are connected to the control input-outputs of the exchange control device, whose polling input is connected to the trigger synchronization input and through a delay element The interrogation output of the exchange control device, characterized in that, in order to increase the system capacity, (T-1) barring tires and (T-1) isolation elements (T are the number of requests priorities) are entered into it, and the prohibition bus (... T-1) is connected to the nth input-output of the prohibition of each exchange control device and through the p-th element of the interchange to the (n-1) -th bus of the prohibition, the first bus of the prohibition through the first element of the interchange connected to the control bus; a switch is inserted into each exchange control device; the input of the request and input-output ION exchange control device connected to the input .. request and with the control input of the switch, respectively, the nth input the control output of the exchange control device (... T-1) is the nth input-output switch, the output of the route memory is connected to the information input of the switch, the output of which is connected to the second inputs of the comparison circuit. 2. The system according to p.-1, differs by that each switch contains the first block (t-1) of the groups of elements And the second block of T groups of elements of And, and the bits of the information input of the switch are connected to the first inputs of elements and groups of elements of the first block, bits of the n-th input-prohibition of the switch of the connection of the p-prohibition of the switch of the connection of the corresponding elements of the n-th group of elements of the first block And the n-th group of elements And (.... T) block, the bits of the control switch input are connected to the first inputs of the corresponding elements AND of the first group of elements AND the second block, 1 switch output of the switch is connected to the outputs of the corresponding elements AND groups of elements AND the second block, the switch request input is connected to the second inputs of the AND elements groups of elements And the first and second blocks. Fi 3 fi 2 FIG L FIG 5 3 3 J