SU1529243A1 - Communication arrangement for multiprocessor computing system - Google Patents

Abstract

The invention can be used to organize the exchange of information between processors having a buffer memory, input / output channels, and RAM modules. The purpose of the invention is to increase the capacity of the device. This aim is achieved in that the device comprises a referee size M ^matrix. H (where M - the number of internal lines devices, H - the total number of subscriber devices) switching block size M ^matrix. H control units, H elements AND, K activation units (where K is the number of subscribers with buffering). 1 hp f-ly, 6 ill.

Description

The invention relates to computing and can be used in multiprocessor computing systems for organizing the exchange of information between processors, which include a buffer memory, input / output channels, and memory modules.

The purpose of the invention is to increase the bandwidth of the device ..

FIG. 1 is a schematic of the device; in fig. 2 is a control block diagram; in fig. 3 - block diagram of activation; in fig. 4 - referee scheme; in fig. 5 is a diagram of the switching unit; Fig. 6 shows timing charts for exchanging information between modules (device subscribers).

The device contains the arbitrator 1, the matrix MVN of the switching blocks 2, the matrix of the control blocks 3, where H is the total number of device subscribers; M is the number of internal highways of the device, N elements I 4, K of activation units 5, where K is the number of subscribers with buffering, a group of information inputs-outputs 6 of the device, output 7 of the sign of activating the external subscriber buffer of the device, input 8 of the sign of the subscriber’s presence with buffering of the device , groups of information I / O 9 switching unit 2, the input 10 of the device request; output 11 of the permission indication of the device, information input-output 12 of the switching unit 2, internal bus 13, group of inputs 14 of the control unit 3 mode, first input 15 of the mode of the control unit 3, first to third outputs 16-18 of the control unit 3, perO1

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and the second inputs-outputs 19 and 20 of the re- versa of the control unit 3, the second input 211 of the control unit re, input 22 k | the output of the 23 elements H 4, the input 24 e | lok 5 activation and the highway 25 letivization.

The control unit 3 includes two triggers 26 and 27j, four elements K-NE 28-31e element 32, two elements

and OR 33 and 34J four elements are NOT three trunk elements (9-41 and delay element 42).

Block 5 of activation forms an ELEHT AND 43 and the element is NOT 44,

Arbitrator 1 - power N nodes 45 ar 5p; aha, element 1, CHI-HE 46, delay element T and NE 48z element, while arbitrary node 45 of the arbitration includes the pk element AND-NOT 49-51, two elements. Both 52 and 53, input 54., Node 45 of arctra a, output 55 of node 45 of arbitration, input 56 of node 45 of arbitration.

The switching unit 2 forms, from the first Boi o through: the seventh elements And 57--63, two elements NOT 64 and 65, two elements And 66 and 675, four groups of elements 1. 68-71, the eighth and ninth elements A 72 and 73 .

Consider the operation of the device when:: with one input-output 6, we call up the shocking (canapes) and called (K; aB: aj) bis operative memory) devices that do not require an actubshizadiya buffer buffer, and to other inputs-outputs 6s outlets 7 :: The devices 8 are connected to the device, all of them are updated with their memory buffer (central processors) g. When connected; x to output 7, it is necessary to send a zero signal to

I To establish a communication, the calling I device sets a single i signal at the input 10 of the request. If solution 1 is free (m eo at inputs 10; there are no interrogation signals from other calling and protecting devices), then it generates an ad signal for output 1: -, the communication solutions which, through the inputs-outputs 6, enters the calling device, and through the inputs-output 9 -; to the input - the outputs of the switching unit 2: and through the information inputs 14 to: the control unit 3 of the given column ,,; By analyzing the signals at I input – output 20 (the bus is occupied by the previous lines) and at inputs 21, the first one is selected from free-internal; THEM TIRES 13s to which it commutes

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- through the switching unit 2, the communication enable signal. The control units 3 connected to the selected internal bus 139 by analyzing the signals at the input-output 19 (subscriber busy line) switch the signal to enable communication from the internal highway 13 to the inputs-outputs 6 of the devices not participating in other exchanges ( inputs-outputs 6 are free). The incoming communication enable signal prepares the free devices to receive the address of the desired called device, prepares the control and switching blocks 3 and 2 (via control inputs 16 and 17) for translating signals between the input-outputs. 6 and internal highway 13,

Upon receipt of a communication resolution signal from arbiter 1, the calling device places an address code of the required called device (for high-level memory, for example, high-order main address bits), an address identifier, an opcode for inputs / outputs 6. The specified information through the free internal highway 13, the inputs-outputs 6 and the corresponding switching blocks 2 enters the free called devices, with the code of the write operation in the operational memory via the highway 25 (activation master), outputs 7 and the corresponding And 4 elements and all activation nodes 5 are sent to all called devices requiring activation of their buffer memory, which ensures that all devices are informed about changes in the RAM.

The called device recognizes its address code and sends to its inputs / outputs 6 a response signal that fixes the necessary connections in the corresponding control units 2 by occupying the internal highway 13 (a single signal appears at the input-output 20) . The response signal, arriving at the calling device, allows the request signal again, releasing the arbitrator 1 for other device requests.

If none of the devices have recognized their address code, then after the predetermined time (time-out) has elapsed, the calling device removes the request signal.

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Next, data and identifiers are exchanged according to the algorithms of the devices.

At the end of the communication session, the calling device, through the inputs-outputs 6, sends a communication end signal, which informs the called device about the end of communication, releases the internal line 13, entering control units 3 belonging to the highway 13 and the input-output 6 of the calling and called devices.

Thus, in a communication device, information is simultaneously transmitted over several trunks between several pairs of devices. The establishment of a link can occur at the same time only for one pair.

Arbitrator 1 can be in two states: Zan t and Free.

The transfer of the arbitrator to the Zanted state occurs for two reasons: when all the highways are occupied and a single signal appears at the output of 18 control units 3 of the last line, which through the NOT 48 element locks all AND 53 elements; when at least one output 10 has a request signal.

If arbitrator 1 is free, then at all outputs 55 nodes 45 arbitration rules

a single signal was introduced, and therefore, at the input of 56 arbitration nodes 45, a single signal.

In order to establish communication, the calling devices establish single signals on the inputs T0 of the respective arbitration nodes 45. Since the elements AND-NO 51 are open, single signals are set at the outputs of the elements AND-NO 50, and the outputs of the elements AND-NE 49 are zero signals. Zero signals from the outputs of the NAND 49 elements, successively pass through the elements of AND 53 and the outputs 55 form a zero signal at the inputs 56 of all nodes 45 of the arbitration (the arbiter goes into the Zan state), prohibiting the reception of other signals from the inputs 10 by locking elements AND-NOT 51, the Zero signal from the output of the element AND-NOT 49 of the first of the nodes 45 of the arbitration, in which the outputs of the elements of the IS-NOT 49 are zero signals, blocks the elements AND 52 of the subsequent nodes 45 of the arbitration. Single signals from the IS-50 outputs prepare the elements AND 52 nodes

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45 arbitration, which received signals from inputs 10 to remove a single signal on inputs 56, Through the delay provided by elements 47 and 46, sufficient for the termination of transients in all elements AND-НЁ 49-51, on the inputs 54 of all nodes 45 arbitration a single signal appears which provides a single signal at the communication resolution output 11 corresponding to the first of the calling devices, since only one of the AND elements 52 is open and the signal from the output of the AND-50 element and the signal from the output 55 of the previous one node 45 rbitrazha.

The communication enable signal on the I / O 6 is fed to the calling device and on the information inputs 14 to all units 3 of the control of this column.

The control unit 3 can be in one of four states depending on the signals at the input-output 20 (busy lines of the previous lines), input-output 19 (subscriber busy lines) and input 21,

If the communication enable signal is received in control unit 3, the line corresponding to which (internal highway 13) is occupied, t, e, on the busy line 20 of the previous lines is a single signal, then AND-NOT element 28 is locked with a zero signal that arrives through the elements NOT 35, AND-NOT. 30 and 31, and no single signal is generated at the outputs 16. The state of control block 3 is blocked,

If the communication enable signal is received in control unit 3, the corresponding internal trunk 13 is free, i.e. the line 18 is filled with a zero signal, but there is a zero signal at input 21 (i.e., at least one of the previous lines is free), then control unit 3 is in the Blocked state, since element AND-NE 28 is locked with zero signal, which comes through the elements and NOT 30 and 31.

If the internal highway 13 is free and input 21 is a single signal (i, e, all previous lines are occupied), then control unit 3 is in the Waiting state and, on arrival, through the inputs 14 of the resolution signal r-in. zi through the elements AND NOT 28, NOT 37

and OR 33 generates a single signal at the output 16 (the control unit 3 goes into the Caller state), the element H-NOT 29 is blocked by the zero signal from the output element, and AND-NOT 28, prepares the trigger 26, at its information input - single signal. Thus, in the column corresponding to the calling device J in the calling state there is one control block 3 corresponding to the first free line s and the rest are in the Blocked state

Having received a single signal at the input 6j, the switching unit 2 by means of the element 72 provides for the communication permission signal.

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the address block locks the AND 58-60 elements, opens the AND 57 element, the AND 69 element group, through which the address of the device being called, the address identifier and the operation code are switched through the inputs-outputs 12 to the internal highway 13,

Through the inputs 22, the address, the address identifier, the communication resolution signal and the write operation signal are fed to the inputs of the H 4 elements, which provide the transfer of the address and address identifier to the activation highway 25 via output 23. If the devices need activation of the buffer memory, then But they support on inputs 8 a zero signal, which through the element is NOT 44

House 9 to the inputs-outputs 12, the Spread opens a group of elements And 43, terminally on the internal highway 13, the communication permission signal is fed through the inputs 15 to all units 3 of the control of this line. The control units 3 3, which are in the Waiting state (i, e, the H-NE 29 elements are open both with the output of the I-PE 28s element and the output of the HE 36 element), ensure output by the elements IS-HE 29, HE 38 and HJQi 34 single signals at output 17 (control blocks 3 go into the Called state) and prepare trigger 27, since at the information inputs there is a single sigram and

If the called property is busy, i.e., the corresponding input-output 19 (subscriber bus) is a single signal, then unit 3 is completely blocked in the state Blocked by means of a zero signal from the output of the HE element 36.

Thus, in the first free line, control block 3 is in the state

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the torus provides the switching of the address and the address code to the outputs 7, the address of the information being changed is thus made available to all devices at the Communication Establishment Time,

In the switching units 2, corresponding to which the control units 3 are in the Called state, the address identifier signal from the internal highway 13 through the inputs-outputs 12 locks the element 61-63, opens the element N 73 and the group of elements 71, through which the address of the device being called The address identifier and the operation code are switched to the inputs-outputs 6 through the inputs-outputs 9 of the switching units 2.

The called device with which the calling is communicating, in response to its recognized address, exposes a response signal to the inputs-outputs 6, which through the inputs 14 goes to the inputs of the flip-flops 27, and through the inputs-outputs 9 to the group the caller generates your block .g cops And 70, At the same time prepared

2 coma Iytacii a single signal at the input, 1 & 5 3. all the remaining blocks 3 of the control of this line, being in the Called 5 state - a single signal at the input 17 of their own switching blocks 2,

The calling device, having received the communication resolution signal from the arbiter 1, puts on the address of the called device, follows its identifier with the address and operation, which -f-iepes the inputs-outputs 9 enter the switching unit 2 and through the inputs 22 to the inputs of the AND element 4 Signal ID 50

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the trigger 27 is set to one state, the response signal from the input-output 9 through the element boundary 70 switches through the input-output 12 to the internal highway 13 Switching unit 2, the control unit 4 of which is in the calling state 5 through the open group of elements 68 switching the response signal from the internal highway 13 to the inputs-outputs 6 through the inputs-outputs 9, and through the inputs 14, the response signal fixes the generation of a single signal to the output 16 through the element 1) 33,

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the address block locks the AND 58-60 elements, opens the AND 57 element, the AND 69 element group, through which the address of the device being called, the address identifier and the operation code are switched through the inputs-outputs 12 to the internal highway 13,

Through the inputs 22, the address, the address identifier, the communication resolution signal and the write operation signal are fed to the inputs of the H 4 elements, which provide the transfer of the address and address identifier to the activation highway 25 via output 23. If the devices need activation of the buffer memory, then But they support on inputs 8 a zero signal, which through the element is NOT 44

opens a group of elements And 43, to

the torus provides the switching of the address and the address code to the outputs 7, the address of the information being changed is thus made available to all devices at the Communication Establishment Time,

In the switching units 2, corresponding to which the control units 3 are in the Called state, the address identifier signal from the internal highway 13 through the inputs-outputs 12 locks the element 61-63, opens the element N 73 and the group of elements 71, through which the address of the device being called The address identifier and the operation code are switched to the inputs-outputs 6 through the inputs-outputs 9 of the switching units 2.

The called device with which the calling is communicating, in response to its recognized address, exposes a response signal to the inputs-outputs 6, which through the inputs 14 goes to the inputs of the flip-flops 27, and through the inputs-outputs 9 - to the elec

the trigger 27 is set to one, the response signal from the input-output 9 through the boundary of the elements And 70 is switched through the input-output 12 to the internal line 13, Switching unit 2, the control unit 4 of which is in the Caller 5 state through the open group of elements 68 switches the response signal from the internal highway 13 to the inputs-outputs 6 through the inputs-outputs 9, and through the inputs 14, the response signal fixes the generation of a single signal to the output 16 through element 1 shih 33,

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setting the prepared trigger 26 to the one state on the control input. In this case, using elements 39 and 40, a single signal is generated at the input-output 20 (busy line of the previous line) and input-output 19 (busy line of the subscriber), and through the element 32, a signal is output to output 20 ,.

Having received a response signal by call-b, the caller removes the address, the address identifier and the signal from input 10, thus releasing the arbiter 1 and activation line 25. In the arbitrator, the output IS-NOT 50 shows a zero signal that prohibits the generation a single signal at output 11, at the output of the NAND 49 element, a signal appears that, through element 51 and output 55, allows the next arbitration node 45 to generate a single signal at output P. If there are no single signals at the information inputs of the arbitrator. then arbitrator 1 goes over Stand Free, i.e. A single signal appears at inputs 53, and a zero signal appears at inputs 54.

Receiving from arbiter 1 through the inputs J4 the zero signal of communication resolution, the control unit 3 of this line, which did not participate in establishing communication, remove single signals from the outputs 17, because their triggers 27 were not installed in the unit state.

Thus, the calling and called device are ready to exchange information through the internal trunk 13 occupied by the corresponding control units 3.

By analyzing the operation code in switching unit 2, the corresponding direction of switching signals from the inputs-outputs 6 and 12 is provided.

During a read operation from the RAM, if the signal at input 16 is single, then through the open elements AND 60 and OR 67 it is possible to switch data from the internal highway 13 through the inputs-outputs 12 and the input element And 7 to the inputs-outputs 9 and dy-exit1 6, if the signal at input 17 is single, then through open elements I.63 and OR 66, data is switched from inputs-outputs 6 through inputs-outputs 9, the element group 30

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com and 69 and the inputs-outputs 12 to the internal highway 13.

During the write operation to the operative memory, if the signal at input 16 is single, then through the open elements And 59 and lUBi 66 data is switched from the inputs-outputs 6 through the inputs-outputs 9, the group of elements And 69 and the inputs-outputs 12 to the internal line 13, if the signal at the input 17 is single, then through the open elements And 62 and 1 Shi 67, data is switched from the internal line 13 through the inputs-outputs 12, the group of elements And 71, the inputs-outputs 9 to the inputs-outputs 6,

During an operation that is not associated with the transfer of data to (from) the RAM, if the signal at input 16 is single, then through the open elements AND 58 and OR 66 the information from the input-output 6 is switched through input-output 9, group elements 69 and the inputs-outputs 12 to the internal highway 13, if the signal at the input 17 is single, then through the open elements AND 61 and OR 67 the information is switched from the internal highway 13 through the inputs-outputs 12, the boundary of the elements 71 , the inputs-outputs 9 to the inputs-outputs 6.

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After performing the specified operation, the calling device sets the end-of-operation signal to the inputs-outputs 6, which is applied to the installation (to O) inputs of the flip-flops 26 and 27, to set them to the zero state (the control unit 3 switches to the Idle state ,. if input 21 is a single signal or in the Blocked state, if input 21 has a zero signal), as well as through the inputs-outputs 9 of the switching unit 2, the group of elements And 70 and the inputs-outputs 12 enter the internal highway And 13, with which through the inputs-outputs 12, the group of elements I. 68 and in One of the outputs 9 is fed to the input-outputs 6 of the called device, informs the called device about the termination of the communication, ensures that the trigger 27 is set to the zero state (the control block 3 switches to the Waiting state, if input 21 is a single signal, or in the Blocked state, if input 21 is a zero signal), ensure the release of the column through element 41,

; Thus, both Devices and the internal RZ highway are released, and the release can occur at once on several trunk lines, Information exchange and termination: in z can occur immediately through echo internal lines and between several pairs of devices. Establishing a connection is possible only between one pair of devices. Simultaneously with the communication setup sequence, information is also transmitted to activate the data in the buffer memory of the multiprocessor computer system.

Claims (2)

Invention Formula I. A communication device of a multiprocessor computing system containing an arbiter and a matrix of size M "fH switching units. Where I is the total number of device subscribers, 11 is the number of internal highways of the device, the pth device input request, where p is 1 ,. .., H and is connected to the p-th information input of the arbiter, the p-th output of which is connected to the p-th output of the device enable feature, the information inputs-outputs of the group of switching units of the p-th column of the matrix of switching units are combined and connected respectively to informational input about the second group of the device, the information input-output of the first switching unit of the e-th row of the matrix of switching blocks where C 1,0 .., M, is connected to the information inputs-outputs of the switching blocks of the C-th row from the second to Nth columns of the matrix of switching units, which differs with. I have the fact that in order to increase the capacity of the device, it contains a matrix of size N "N control blocks, H elements I and K of the activation blocks where K is the number of subscribers with buffering, while the information inputs-outputs of the p-th device group are connected to the inputs of the group mode of control units of the p-th column of the matrix block. control and to the inputs of the pth element I, and the th input of the sign of the presence of a subscriber with device buffering, where a. 1K connected to the first the input of the th block of activation, exit j5 ten 20 25 thirty 35 40 45 50 55 which is connected to the th output of the sign of activation, and device subscriber buffer, informational input-output of the Nth switching unit. The Cth row of the switching unit matrix is connected to the first inputs of the control unit mode. The Cth row is the control unit matrix, the first input-output of the control unit of the C-th row of the first column of the matrix of the control blocks connected to the first inputs-outputs of the mode of the control blocks of the C-th row of columns from the second to the second input of the mode of the control block of the first row of the p-th column of the matrix of control blocks connected to the second inputs-outputs of the control unit mode from the second to the M-th row of the p-th column of the matrix of control blocks; p-th input of the device mode is connected to the second input of the mode of the control block of the first row of the p-th column of the matrix of control blocks; first output block control of the b-th row of the p-th column of the matrix of control blocks, where b 1,.,., M-1, is connected to the second input of the mode of the control block (b + 1) - the row of the p-th column of the matrix of control blocks, the second and the third outputs of the control unit of the Cth row of the pth column of the matrix of control units Yuchen to the first and second control inputs of the switching unit of the Cth row of the pth column of the switching unit matrix, the first output of the control unit of the first column of the Mth row of the matrix of control units connected to the input of the arbiter lockout, moves the I elements from the first through N combined with MOHTAJIfflOFO 11PI and connected to the second inputs of the activation units. 2. The device according to claim 1, about tl and - that the control unit contains two triggers, four NOT elements, four AND-NOT elements, two RShN elements, three main elements, the And element and the delay element, the first input the output of the control unit is connected to the first input of the element I, to the input of the first element NOT and to the output of the first main element, the second input / output of the mode of the control unit is connected to the input of the second element. NOT to the outputs of the second and third main elements, the first input of the control unit mode connected to the first input of the first NAND element, the output of which is connected to the input of the third element NOT and to the first input of the second element NAND, the output of which is connected to the second input of the first element N – NO, to the input of the fourth element NOT and to the first input of the third element AND-NOT whose output is connected to the second input of the second element AND-NOT, the second input of the control unit mode is connected to the first input of the fourth element AND-NOT and to the second input of the AND element whose output is connected to the first output of the control unit, the first input of the gr ppy which is connected to the third input of the second elements; This NID, the second input of the group mode of the control unit is connected to the sync inputs of the first and second triggers, the third input of the group mode of the control unit is connected to the input of the delay element, the output of which is connected to the installation inputs to the first and second triggers, the output of the first element is NOT connected to the second input of the fourth NAND element, the output of which is connected to the second input of the third element NAND, the output of the second element is NOT connected to the third input of the first element NAND, the output of the third element is NOT connected to the information input of the first trigger and to the first input of the first element OR, the output of the fourth element is NOT connected to the information input of the second trigger and to the first the input of the second OR element, the output of the first trigger, is connected to the second input of the first OR element and to the input of the third main element; the output of the second trigger is connected to the second input of the second OR element and to the inputs of the first and second of the second and first elements OR are connected respectively to the second and third control unit, each activation unit contains a NOT element and an AND element, the first and second inputs of an activation block are connected respectively to the input of the HE element and to the first AND element , the second input of which is connected to the output of the element NOT, the output of the element AND is connected to the output of the activation unit. "V "L eight f7 25 55 G-- I LL w Fi.e 55 five .I 0t / e / 0 7 /  cu.zHuf, cKOMMtjmui} o6uHHt, iLL from input 11 not a minute 13 NOL KOHei {operations. FIG. 6