SU1359783A1 - Commutation system - Google Patents

Abstract

The invention relates to computing, solves the problem of reducing the system recovery time in the event of line information bus failures. The switching system contains switches 1 interconnected and with subscribers 2 information buses, exchange control devices 4, connected with subscribers 2 address buses, and between themselves and with the recovery unit 9 the polling line. The invention consists in the introduction of a recovery unit 9 connected to two switches 1 by information buses, also connected to reset circuit exchange control devices 4 and a polling line, and to all switches to fault indication lines. This allows you to implement the procedure for the operational restoration of any information bus in the event of a failure of the information line included in the bus. 5 il. with jO (L 00 ate from 00 00 (Figure 1

Description

one

The invention relates to computing and can be used in the construction of information exchange systems between computers or modules of multiprocessor computer systems.

The purpose of the invention is to reduce the recovery time of the system in case of failures of information bus lines.

Figure 1 shows the block diagram of the switching system; Figures 2-5 are functional diagrams of the exchange control device, recovery unit, switch and control unit, respectively.

The switching system (Fig. 1) contains K switches 1 connected by a melada by itself and with H subscribers 2 through

means of information bus Z. Ust-20 dami to the inputs of the element OR NOT. The exchange control terminals 4 provide the establishment of a connection between subscribers 2 by issuing signals to certain control lines 5. Each information bus 3 corresponds to a control line j, the presence of a signal on which the information bus B is busy. To streamline the process of establishing connections between different pairs of subscribers 2 all exchange control devices 4 are connected by a closed polling line 6, through which a pulse is transmitted allowing device 4 to control switching. h

The subscriber 2 is connected to the exchange control device 4 of the address PC 7 and the request chain 8, which serve to issue the address of the recipient 2 to the addressee and the request to establish a connection.

The recovery unit 9 connected to the switches 1 by the failure indication lines 10 provides the identification of the number of the line 3 that failed on some information bus and the connection of the backup line instead. The signal in the reset circuit 11 causes the connection between the subscribers 2 to be broken for the recovery time. The start block 12 generates a pulse that begins to circulate in the polling line.

Switches 1, by signaling on control lines 5, allow to connect information buses 3, the sequence of which included in the route allows subscribers 2 to exchange data.

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. dy of the element m i are connected to the m m memory output of 13 routes and to the m th line 5 of the control. A unit at the output of the comparison circuit 14 appears, 25 if the output of all elements is E and Zero This condition is possible if bus 3 entering the route is free, which is indicated by zero on the mth line 5 or bus 3 (even Zana Zha) in this route is not included - at the memory output of m 13 routes zero.

Trigger 16 provides route code via a group of 17 elements AND on line 5 of the control. Element AND 15 allow the em to set the trigger 16 to 1 with the arrival of signals from the comparison circuit 14 on the circuit 8 of the request of the interrogation line 6. The trigger 16 is reset when the signal in the circuit 8 of the request disappears or when a signal appears in the circuit 11 of the reset . The request circuit 8 is connected to the inverse of the trigger input 16, which is set to zero. Delay element 18 is designed to delay the signal on the polling line by the transient time in the system elements.

The recovery block (FIG. 3) contains a register 19, an adder 20 errors, four flip-flops 21-21, an encoder 22, four AND elements, four delay elements 24-24, three OR 25-25 elements, a group of 26 And elements, a group 27 elements OR, node 28 memory routes, node 29 prohibition, multiplexer 30.

Register 19 is connected by counting inputs to the 3 P data bus connecting the recovery unit 9 with a com

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The exchange control device 4 (Fig. 2) contains a memory of 13 routes, a comparison circuit 14, an AND element 15, a trigger 16, a group 17 of Hf elements. delay element 18. The memory 13 routes stores the positional codes of the routes from this subscriber 2 to all other subscribers 2. The unit in the fifth position from the second cell means that information bus 3 enters the route from subscriber 2 to subscriber f. Access to the memory 13 of the routes is made at the address set on the address bus 7, and in the presence of a signal in the request chain 8.

The comparison circuit 14 determines the possibility of capturing the route. It contains the elements And the connected output0

five

. dy of the element m i are connected to the m m memory output of 13 routes and to the m th line 5 of the control. The unit at the output of the comparison circuit 14 appears, 5 if at the output of all the elements E is zero. Such a state is possible if bus 3 entering the route is free, which is indicated by zero on the mth line 5, or bus 3 (even if it is busy) is not included in this route — on the memory output of the route 13 routes zero.

Trigger 16 provides route code via a group of 17 elements AND on line 5 of the control. Element I 15 assigns the em- to set the trigger 16 to 1 with the arrival of signals from the comparison circuit 14 over the circuit 8 of the request of the interrogation line 6. The trigger 16 is reset when the signal in the circuit 8 of the request disappears or when a signal appears in the circuit 11 of the reset . The request circuit 8 is connected to the inverse of the trigger input 16, which is set to zero. Delay element 18 is designed to delay the signal on the polling line by the transient time in the system elements.

The recovery block (FIG. 3) contains a register 19, an adder 20 errors, four flip-flops 21-21, an encoder 22, four AND elements, four delay elements 24-24, three OR 25-25 elements, a group of 26 And elements, a group 27 elements OR, node 28 memory routes, node 29 prohibition, multiplexer 30.

Register 19 is connected by counting inputs to the 3 P data bus connecting the recovery unit 9 with the com

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mutator 1, and is intended for pri-. The test information and the formation of the number of the failed line in the data bus 3 is used. The adder 20 errors allows you to determine the number of failed lines. It has a single sign output and a multiple error sign output. The signal on the first of these means the possibility of 41d and on the second the impossibility of recovery, since each information bus 3 contains only one backup line, replacing any of the main lines after a failure. The presence of more than one failed line in the data bus 3 qualifies as a fatal failure.

The first 2V and the second 21 triggers serve to fix the fact of a disposable 20 or unrecoverable failure. The first element AND 23, in the case of only a recoverable failure, allows the number or address of the failed line to be output from the encoder 22 through a group of 26 AND elements, through a group of 27 OR elements into the information bus connecting the recovery unit 9 with switch 1. Simultaneously from the output of the AND 23 element In-line information

bus 3, a signal is issued allowing the address to be received by those switches that cover the failed bus 3.

Route memory node 28 is designed to store route codes from recovery block 9, passing through different switches 1 and ending in block 9. Each route allows test information to be transmitted through switching system elements that include the failed bus 3. The failed bus number 3 enters lines 10 for indication of failures, calls to the input of node 28. The recovery route code is stored in node 28 in the same form as in memory 13 of the routes.

The presence of a unit on the fault indication line 10 indicates the need for recovery. The OR element 25 allows the system to be put into recovery mode: its output is connected to the reset circuit 11 and to the selector from

the third element, And 23, defines the process of the restoration. The output of the element 23 is connected to the reset inputs of the register 19, the flip-flops 21 and 21, to the synchronization input of the trigger 21, and to the input of the distributor consisting of series-connected delay elements 24.

, installation input to the output element

Trigger 21

the second is connected to

OR 25, and the reset input is with

delay 24, designed

to control multiplexer 30.

15 In the recovery mode, the recovery route code from node 28 is transmitted to the output of the typelexer 30, and in normal operation, the code from the inhibit node 29.

Prohibition node 29 allows you to block data transmission on those information buses 3 in which not one, but several lines failed. The first, second and third inputs of the prohibition node 29 are connected to the fault indication lines 10, respectively, to the outputs of elements S1I 25 and I 23. It contains a register in which each trigger has a control input and a reset synchronization input connected to the corresponding bit of the first input node 29, the synchronization input of the installation to the second, and the reset input to the third inputs of the prohibition node 29.

Trigger 21 provides issuance

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in the information bus 3 test actions - at the beginning of the unit, and then zeros on all lines. It is connected by an output to the second input of each element OR bust 27.

The output of the delay element 24 is connected to the discharge of the reset indication of the information output of the recovery unit 9, which, upon completion of the restoration, resets in the switches 1 triggers that are locked from the switch.

Switch 1 (FIG. 4) contains a control unit consisting of AND 31 elements, a first group of 32 multiplexers, a group of 33 demultiplexers, a second group of 34 multiplexers and control units 35. To the entrances of each element35

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Elements And 23 and 23 of the direct line And 31 are connected a pair of lines 5 but also through the inverter, respectively. control, the inverse output of its Fourth element And 23 serves for the unity with the inputs of those elements And 31,

connected to any of the lines

transmission of a polling pulse through the element OR 25 to the output of block 9, and

5 of this pair. This allows the exception of 7834

the third element, And 23, defines the principle of the recovery process. The output of the element 23 is connected to the reset inputs of the register 19, the flip-flops 21 and 21, to the synchronization input of the trigger 21, and to the input of the distributor consisting of series-connected delay elements 24.

, installation input with the output element

Trigger 21

the second is connected to

OR 25, and the reset input is with

delay 24, designed

to control multiplexer 30.

In the recovery mode, the route code, that recovery from the node 28, is transmitted to the output of the speedlexer 30, and in the normal operation mode, the code from the ban node 29.

Prohibition node 29 allows you to block data transmission on those information buses 3 in which not one, but several lines failed. The first, second and third inputs of the prohibition node 29 are connected respectively to the fault indication lines 10, to the outputs of the elements S1I 25 and I 23. It contains a register in which each trigger has a setup input and a reset synchronization input connected to the corresponding bit of the first input of the node 29, the installation synchronization input to the second, and the reset input to the third inputs of the prohibition node 29.

Trigger 21 provides issuance

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in the information bus 3 test actions - at the beginning of the unit, and then zeros on all lines. It is connected by an output to the second input of each element OR bust 27.

The output of the delay element 24 is connected to the discharge of the reset indication of the information output of the recovery unit 9, which allows, upon completion of the restoration, to reset the triggers in the switches 1, which register failures.

Switch 1 (FIG. 4) contains a board unit consisting of elements 31, a first group of 32 multiplexes, a group of 33 demultiplexers, a group of 34 multiplexers, and a control unit 35. To the entrances of every ele

5 of this pair. This eliminates the connection of new information buses 3 with the pair of buses 3 that were previously connected in switch 1. The first group of 32 multiplexers connects the information bus 3 in accordance with the signals from the control unit. The second group of 34 multiplexers provides modulator 36 modulo two, the inverse output of which is connected to the trigger input 37, and the inputs of the information bus 3, the vibrator 38 and the OR element 39. The trigger 37 is the output of the control unit 35, and sa inputs are connected to the one-shot 3

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connects a backup line with a fault localization circuit 40, a hundred failed main line in the information bus 3. Each multiplexer 34 contains an address register connected by inputs to the outputs of multiplexer 32, and outputs to the inputs of the decoder, the outputs of which are connected to the control inputs of the I-IPI element . The information inputs of the AND-OR element are connected to the outputs of multiplexer 32, and the output is connected to the backup line. The synchronization input of the address register is connected to the output of the element I, the first input of which is connected to the reception line, and the second to the control; its input to the multiplexer 34 connected to the corresponding line of the information bus 3. The receiving line from the recovery unit 9 receives the signal , resolving reception of the address.

The demultiplexer 33 provides switching of the backup line to the corresponding output instead of the main line. It contains the address register, the inputs of which are connected to the information bus 3, and the outputs to the inputs of the decoder. The outputs of the demultiplexer are the outputs of the OR elements combining pairs of elements I.

To the first inputs of elements And ka hell

pairs are connected to the main and backup lines of the information bus 3,

and to the second inputs directly and

through the inverter, the corresponding output of the decoder. The synchronization input, the address register is associated with the output

element And, the first input of which

connected to the receive line, and the second to the control input of the demultiplexer 33 and to the corresponding line

information bus 3. At the specified

line control signal is transmitted

in the neighboring switch 1, where it includes the operation of the multiplexer 34.

The control input of demultipexor 33 is connected to the display output.

control unit 35, which allows

you crash information bus 3.

The control unit (FIG. 5) contains a summatic modulator 36 modulo two to detect the failure of information bus 3, which includes, in my information, a control line with odd evenness. Three Ger 37 records the fact of failure. The vibrator provides for the setting of the gera 37 to its initial state; 40, together with elements OR 3, permits localization of the failure with up to one information 3. If there is no target 40, failure causes installation of 1 Gerov 37 in control units 35, 25 35, etc., connected to bus 3, 3, ..., the control units that enter the route do not fix the failure, but the fact of the code distorted in the bus 3. The trigger exit trigger Cig 37 in block 35 trol, propagating through the center, sets the triggers of the 3 remaining blocks, the control, to zero. In retreat, only control unit 35 controls actual tire failure.

Circuit 40 for localization of the fault and the main bus 3 is connected to the discharge of the indication that the information output of the block 9 is reset in

The switching system functions as follows.

In the absence of failures, provide data exchange between the subscriber. In the memory, 13 routes of all exchange control devices 4 are assigned to routes establishing connections between subscribers 2. At node 28 and routes, route codes used for transmitting the dough are taken after the system is turned on. starting to circulate along line 6 of the survey. To the subscriber, the initiator 2 transmits via the address bus 7 the address of the desired subscriber, and via the W chain the request signal, the live time of the exchange. From pa 13 routes read; tc code of mata, analysis is possible its capture, if it exists

35

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Matrix 36 is modulo two, the inverse output of which is connected to the setup input of the trigger 37, and the inputs to the lines of the information bus 3, the single vibrator 38 and the OR element 39. The output of the trigger 37 is the display output of the control unit 35, and the reset inputs , sa are connected to the one-shot 38 and

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with a chain of 40 localization of failure,

Modulo 36 admits detection of a data bus 3 failure, which includes, in addition to the information, a check-out line of odd evenness. The trigger 37 captures the fact of failure. A single vibrator ensures that trigger 37 is reset; the chain 40 together with the elements of OR 39 allows localizing the failure with an accuracy of one information bus 3. In the absence of a goal 40, a bus failure causes installation of 1 flip-flops 37 in control units 35, 35, 5 35, etc. connected to tires 3, 3, 3, ..., included in the route. In this case, the subsequent control units will not fix the failure, but the fact of transmission of the code distorted in the bus 3. The signal from the output of the trigger 37 in the control unit 35, propagating along the circuit 40, establishes the triggers 37 in the remaining blocks, the control, to zero. As a result, only the control unit 35 records the actual failure of the bus Z.

The information bus 3 localization circuit 40 is connected to the discharge of the indication of the information output of the block 9 to be reset.

The switching system operates as follows.

In the absence of failures, data is exchanged between subscribers 2. In the memory 13 routes of all devices 4 of the exchange control, route codes are entered that establish the connection between subscribers 2. In section 28 of the route memory there are route codes used for transmitting the tests. After the system is turned on, start-up unit 12 generates a signal starting to circulate along polling line 6. The initiator subscriber 2 transmits the address of the desired subscriber 2 via the address bus 7, and the request signal, held during the exchange time, via the S link. From the memory 13 routes are read; tc route code, an analysis is made of the possibility of its capture, if it exists.

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with the arrival of a pulse on line 6, the device issues a route code on line 5 of the control. Switches 1 connect the route, and subscribers 2 exchange data. After the exchange, the initiator subscriber removes the signal in the request chain 8 and the connection is destroyed. In the event of a failure of the information bus, the 35 control fixes it and, via the Yu line, a failure indication reports it

20

in block 9 recovery. On the reset circuit 11 of block 9, a signal is issued, which resets the flip-flops 16 in all the bus interconnection control devices 4. All routes are temporarily destroyed. With the arrival of a pulse on line 6

The survey in recovery block 9 begins the recovery cycle, which includes the steps of laying out an annular route from block 9, passing through from the bus 3, issuing test effects and fixing their results, analyzing the results and eliminating the consequences of failure.

The ring route is laid by issuing a route code from memory node 28 through multiplexer 30 after setting to 1 flip-flop 21. At the same time, register 19 and flip-flops 21 and 21 are reset. Switches t connect the information buses 3 according to the code on control lines 5 . Route

The recovery of the failed bus 3 is performed by switching on the backup line. For this, the recovery unit 9 from the outputs of the encoder 22 provides the address of the failed link, which is transmitted along the route and entered into the address registers of the multiplexer 34 and the multiplexer 33 located in the adjacent switches 1 and span 3. The insertion is possible, since their control inputs receive a signal from the display output of the control unit 35. The termination of the use of the tire 3 is effected after the installation of the trigger 21, which prevents the register from the prohibition node 29 from being reset. Therefore, it stores the unit recorded from line 10

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thirty

fault indications. Upon completion of the recovery cycle, this unit is output through multiplexer 30 to control line 5, which indicates that it is impossible to capture information

us 3.

The occurrence of a unit at the output of delay element 24 allows the reset signal to be reset along the route by restoring the zero trigger 37 The recovery cycle is completed. Impulse in line 6

laziness and install in block 35 control

DP of the transmission of test effects of the scanner triggers the devices to operate; the failed bus is prepared. The distributor consisting of delay elements 24 starts operating. Set to 1 trigger 213, and

4 exchange control. The connections between subscribers 2 are reestablished and the exchange continues.

40

the invention

through a group of 27 OR elements, the first test is transmitted to the 7th Formula to the Shrut — a single switching system containing Kits across all lines. After resetting the trigger switches, H of the control device 21 is transmitted by the interchange, the start block, And the second test is zeros. The results of both of the structural switches I / O switches (n L) are the corresponding information inputs of the system, connected to the subscribers, the other information inputs 50

The stations are fixed in register 19. On the inverse outputs of its triggers, units appear in those bits that correspond to the failed lines in bus 3. It is assumed that two types of failures are possible - constant zero or unit constant on the line.

An analysis of the results of the check allows to establish whether the failure is recoverable or not. If the error adder 20 detects the presence of a single error, i.e. single failure, then the failed bus 3 can be recovered. .If multiple failure is detected

five%

the switch outputs of the switches are interconnected, the address input and the input request of the Nth exchange control device (H1, ... n) are the Nth address and system request inputs from the Nth subscriber, respectively; the input / output controls of the devices exchange control systems are combined and connected via control lines to the corresponding control inputs.

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g tires

lines, it is necessary to prohibit further use of the bus. In the first case, the trigger 21 will work, and in the second - the trigger 21.

The recovery of the failed bus 3 is performed by switching on the backup line. For this, the recovery unit 9 from the outputs of the encoder 22 provides the address of the failed link, which is transmitted along the route and entered into the address registers of the multiplexer 34 and the multiplexer 33 located in the adjacent switches 1 and span 3. The insertion is possible, since their control inputs receive a signal from the display output of the control unit 35. The termination of the use of the tire 3 is effected after the installation of the trigger 21, which prevents the register from the prohibition node 29 from being reset. Therefore, it stores the unit recorded from line 10

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0

fault indications. Upon completion of the recovery cycle, this unit is output through multiplexer 30 to control line 5, which indicates that it is impossible to capture information

us 3.

The occurrence of a unit at the output of delay element 24 allows the reset signal to be reset along the route by restoring the zero trigger 37 The recovery cycle is completed. Impulse in line 6

laziness and install in block 35 control

 polling triggers devices

polling triggers devices

4 exchange control. The connections between subscribers 2 are reestablished and the exchange continues.

 polling triggers devices

40

the invention

7 Formulas switching system containing K switches, H controllers of the exchange, start unit, with n „„ formation inputs-outputs of switches (nN) are the corresponding information inputs-outputs of the system connected to subscribers, other information inputs50

five%

the switch outputs of the switches are interconnected, the address input and the input request of the Nth exchange control device (H1, ... n) are the Nth address and system request inputs from the Nth subscriber, respectively; the input / output controls of the devices exchange control systems are combined and connected via control lines to the corresponding control inputs.

(

switches, the output of the start-up unit is connected to the polling input of the first exchange control device, the polling output of the P-paging control device (p I, .., H - 1) is connected to the polling input of the (P + 1) -th exchange control device, each switchboard contains a control unit, the first group of multiplexers, a control unit, the control inputs, the switch are connected to the inputs of the logic conditions of the control unit, the outputs of which are connected to the corresponding control inputs of the multiplexers of the first group, the display outputs The control module is connected to the corresponding switch display outputs, and the control failure localization outputs are connected to the corresponding information bus failure localization lines, which, in order to reduce the system recovery time in case of information bus lines failures, a recovery block containing register, error adder, encoder, four flip-flops, three OR elements, four AND elements, four delay elements, AND group of elements, OR group of elements, route memory node, prohibition node and An ultiplexer, the polling output of the Nth exchange control device is connected to the polling input of the recovery unit, whose polling output is connected to the start-up block of the indication inputs of the recovery unit are connected to the corresponding commutator display outputs, the information input of the recovery unit is connected to the information output of one switch, and the information output of the block was restored

nor is connected to the information input of the recovery unit, with the second

The remote control of the other switch, the output of the reset indication of the recovery unit is connected to the reset inputs of each exchange control device, the recovery route outputs of the recovery block are connected to the corresponding control input / output bits of the exchange control devices, the information input of the reset unit is connected to the counter inputs of bits, inverse .outputs which are connected to the corresponding inputs of the adder-error and encoder, the outputs of the signs of single and multiple

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55

the input of the second element AND, with the reset input of the fourth trigger, and with the first input of the third element OR, the output of the fourth element AND is connected to the second input of the third element OR whose output is connected to the polling output of the recovery unit, the output of the second element OR is connected to the third input of the first element And the output of which is connected with the discharge of the reception information output sign of the recovery unit and with the first inputs of the elements AND of the group, the outputs of the encoder are connected to the second inputs

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20

the errors of the error adder are connected to the setup inputs of the first and second triggers, respectively, the direct output of the first trigger is connected to the nep-i first input of the first element, And the inverse output of the second trigger is connected to the second input of the first element Nick the first input of the second

10 AND elements, indication inputs of the recovery block i are connected to the corresponding address inputs of the route memory node, to the inputs of the first OR element and to the bits of the first input of the inhibit node, whose outputs are connected to the first information inputs of the multiplexer, the second information inputs of which are connected to the output of the route memory node, the output of the first element OR is connected to the second input of the inhibit node, to the setup input of the fourth trigger, to the first direct and inverse inputs of the third and fourth elements AND to the output

25 block reset, recovery, the polling input of the recovery block is connected to the second inputs of the third and fourth elements AND, the output of the third element AND is connected to the synchronization input of the fourth trigger, to the reset inputs of the first and second triggers and to the input of the first delay element whose output connected to the setup input of the third trigger and to the input of the second delay element, the output of which is connected to the first input of the second element OR to the reset input of the third trigger and to the input of the third delay element, you the stroke of which is connected to the second input of the second OR element and to the input of the fourth delay element, the output of which is connected to the discharge of the reset sign of the information output 35

40

 of the recovery unit, with the second

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55

the input of the second element AND, with the reset input of the fourth trigger, and with the first input of the third element OR, the output of the fourth element AND is connected to the second input of the third element OR whose output is connected to the polling output of the recovery unit, the output of the second element OR is connected to the third input of the first of the And element, the output of which is connected with the discharge of the reception indicator of the information output of the recovery unit and with the first inputs of the AND elements of the group, the outputs of the encoder are connected to the second inputs

I will give the corresponding elements AND, the outputs of which are connected to the first inputs of the elements of the OR group, the output of the third trigger is connected to the second. the inputs of the elements OR groups, the outputs of which are connected to the bits, the address of the information output of the recovery unit, the output of the second element AND are connected to the third input of the prohibition node, the direct and inverse outputs of the fourth trigger are connected to the first and second control inputs of the multiplexer, the outputs of which are connected to the outputs the recovery path of the recovery block, and the second group of multiplexers is entered into the 4 each switch

9783

12

and a group of demultiplexers, each switchboard information input-output is connected to the outputs of the corresponding multiplexer of the second group and to the inputs of the corresponding group demultiplexer, the outputs of the group's multiplexer are connected to the inputs of the corresponding control units and the information inputs of the corresponding multiplexers of the first group, the outputs are connected to the information the inputs of the corresponding multiplexers of the second group, 5 the display of the display of the control unit is connected to the control inputs of the corresponding tive demultiplexers and multiplexers of the second group.

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T

(rig 2

FIG. five

Claims (1)

SUMMARY OF THE INVENTION A switching system comprising K switches, H exchange control devices, a start-up unit, with η 45 information inputs and outputs of the switches (p, H) being the corresponding information inputs and outputs of the system connected to the subscribers, the rest information inputs 50 the outputs of the switches are interconnected, the input of the address and the request input of the N-th exchange control device (H = 1, ... n) are the N-th inputs of the address and the request of the system from 55 N-th subscriber, respectively, the inputs of the control devices Ia exchange poryazryadno combined and connected through a control line to the respective control inputs of the switches, the start block output is connected to the input of the first polling communication control device, the output P th polling ob- control device _(mepom (p = 1 ,, H -. 1) connected to the polling input of the (P + 1) -th exchange control device, each switch containing a control unit, a first group of multiplexers, a control unit, while the control inputs of the switch are connected to the inputs of the logical conditions of the control unit, the outputs of which are are connected to the corresponding control inputs of the multiplexers of the first group, the indication outputs of the control unit are connected to the corresponding indication outputs of the switch, and the failure localization outputs of the control unit are connected to the failure localization lines of the corresponding information buses, characterized in that, in order to reduce the system recovery time in case of line failures information buses, it contains a recovery unit containing a register, an error accumulator, an encoder, four triggers, three OR elements, four AND elements, four th delay element, and a group of elements, elements of group OR, routes the memory node, the node za-. and a multiplexer, and the polling output of the Nth exchange control device is connected to the polling input of the recovery unit, the polling output of which is connected to the input of the start block, the indication inputs of the recovery unit are connected to the corresponding outputs of the indication indication of the switches, the information input of the recovery unit is connected to the information output one switch, and the information output of the recovery unit is connected to the information input of another switch, the output of the reset reset sign is connected it is connected to the reset inputs of each exchange control device, the outputs of the recovery path of the recovery unit are connected to the corresponding bits of the inputs and outputs of the control of exchange control devices, the information input of the recovery unit is connected to the counting inputs of the bits whose inverse outputs are connected to the corresponding inputs of the error adder and the encoder, the outputs of the signs of a single and multiple errors of the error adder are connected to the installation inputs of the first and second triggers, respectively, direct output first trigger connected to per-! to the input of the first AND element, the inverse output of the second trigger is connected to the second input of the first AND element and to the first input of the second AND element, the indication inputs of the recovery unit are connected to the corresponding address inputs of the route memory node, to the inputs of the first OR element, and to the bits of the first input of node 15 prohibition, the outputs of which are connected to the first information inputs of the multiplexer, the second information inputs of which are connected to the output of the route memory node, the output of the first 20 OR element is connected to the second input of the node prohibition, to the installation input of the fourth trigger, to the first direct and inverse inputs of the third and fourth elements And and to the output 25 of the reset unit, recovery, the polling input of the recovery unit is connected to the second inputs of the third and fourth elements And the output of the third element And is connected to the synchronization input30 the fourth trigger, with inputs for resetting the register, the first and second triggers and with the input of the first delay element, the output of which is connected to the installation input of the third 35 trigger to the input of the second delay element, the output of which is connected to the first input of the second OR element with the reset input of the third trigger and to the input of the third delay element ₄ Q ki, the output of which is connected to the second input of the second OR element and to the input of the fourth delay element, output which is connected to the reset discharge characteristic information you d ₄ stroke recovery unit, a second input of the second aND gate, a reset input of the fourth flip-flop and the first input of the third OR gate, the output of the fourth aND element is connected g, _n to the second input of the third element □ and OR, whose output is connected to the polling output of the recovery unit, the output of the second OR element is connected to the third input of the first AND element, the output of which is connected to the discharge sign of the information output of the recovery unit and with the first inputs of the elements AND groups, the encoder outputs are connected to the second input 1 1 I will give the corresponding AND elements, the outputs of which are connected to the first inputs of the OR elements of the group, the output of the third trigger is connected to the second inputs of the OR elements of the group, the outputs of which are connected to the bits of the address of the information output of the recovery unit, the output of the second AND element is connected to the third input of the prohibition node, direct and inverse outputs of the fourth trigger are connected to the first and second control inputs of the multiplexer, the outputs of which are connected to the outputs of the recovery route of the recovery unit, and in each comm a second group of multiplexers and a group of demultiplexers are introduced; each information input-output of the switch is connected to the outputs of the corresponding multiplexer of the second group and to the inputs of the corresponding demultiplexer of the group, the outputs of the demultiplexer of the group are connected to the inputs of the corresponding control units19 and to the information inputs of the corresponding multiplexers of the first group, the outputs of which are connected to respective data inputs of the multiplexers of the second group ₁₅ outputs the display unit cont I connected to the control inputs of the respective multiplexers and demultiplexers of the second group. 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