GB1570113A - Telecommunication switching systems - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO TELECOMMUNICATION SWITCHING SYSTEMS (71) We, STANDARD TELE PHONES AND CABLES LIMITED, a British Company of 190 Strand, London W.C.2. England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to electronic systems employing multiplicated logic units with majority decision voting techniques used to give usable outputs when faults occur.

Such systems are used, inter alia, in automatic telecommunication exchange systems, and in such systems it is desirable that when a fault occurs it is located and rectified. This is necessary to avoid the risk of the operation being unsettled by the presence of two simultaneous faults. An object of the invention is to provide a checking arrangement which enables such faults to be at least partially located.

According to the present invention there is provided an electronic data handling system in which data handling units are replicated, there being n of each said unit (n 3 3) working in parallel on the same data, in which the outputs of all of said n units at each stage of the system are compared and the output of the stage derived on the basis of a majority voting technique, in which for test purposes the units are sequentially selected with the selection process in respect of each said unit to be tested involving the stimulation of the said unit to perform a defined operation, and in which the results of the operations thus initiated for test purposes from all of the replicated units are checked so that if a fault occurs its location can be determined.

An embodiment of the invention will new be described with reference to the drawings accompanying the Provisional Specification in which Fig. 1 is a simplified schematic of a telecommunication system to which the invention is applicable, while Figs. 2 to 8 are simplified schematics explanatory of the invention.

The invention is described herein as applied to a message transmission system which forms part of a large scale telecommunications switching system, and is for the determination as to which replaceable unit in a system in which the logic is multiplicated, and which uses majority voting techniques and forms part of the message transmission system, contains a malfunction.

As applied in the above systern, the invention is used for fault detection in a PCM switching arrangement of the T-S-T (Time Space-Time) type, Fig. 1, which uses in the main three-level logic, i.e. each of the main logic units is triplicated. This arrangement serves a large number of incoming and outgoing junctions, and typically has 1000 highway printed circuit cards, e.g. 1, each of which serves one pair of PCM highways (incoming and outgoing). Each such highway operates at 2.048 Mb/s and serves 31 channels including a signalling channel.Associated with each group of up to sixteen highway cards, which are not triplicated, is an incoming time switch which is at least in part triplicated, a selection control formed by a control store which is also triplicated and an outgoing time swirch which is also triplicated. As is usual in PCM systems these time switches are fundamentally storage arrangements into which PCM combinations are written at their time of arrival and from which they are read out at an intended time of departure. In Fig. 1, Al, A2 and A3 are the incoming time switches; B1, B2 and B3 are the control stores which store data "telling" when the time switches are to be read from or written into; and C1, C2 and C3 are the outgoing time switches.As will be seen, the PCM switching arrangement also includes a space switch for switching between individual ones of the junctions served by the system, but this switch is not shown as it would needlessly complicate the drawings.

As mounted at a switching centre, the units Al, B1 and C1 fit on one shelf of a rack close to a shelf carrying units A2, B2 and C2 and another shelf carrying A3, B3 and C3.

Further, there are sixteen replaceable units located on each shelf, plus the power supplies.

If a failure occurs in the triplicated area of the system, the majority voting technique used ensures that the failure is out-voted and the logic continues to operate correctly, at least as "seen" by the rest of the system. To ensure that the triplicated logic can operate correctly when a component failure occurs it is necessary that failed components be replaced as soon as possible, so that the pro- ability of two failures being simultaneously present is acceptably low. enhles the loca The present arrangement~enables tion of a faulty component to be pin-pointed to one replaceable unit in a large proportion of such faults, and assists in locating a fault where it cannot be so closely pin-pointed.

In the present arrangement fault location is based on the comparison of waveforms from the n similar units - in Fig. 1 from three units. A scanner card is mounted on one of the three shelves which carry the various replaceable units of the switching unit shown in Fig. 1, and the equipment on all three shelves is referred to herein as a traffic unit There is therefore one such scanner card with each of the traffic units considered: in the system part of which is shown in Fig. 1 there are 64 such units and hence 64 scanner cards. Also provided are similar scanner cards for the associated (and triplicated) units D1, D2 and D3 (not shown), which are 64 X 64 time divided space switching units, each of which has 9-wire crosspoints since 9 wires are switched in parallel.The use of 9 wires follows from the use of 8-bit PCM codes plus an extra bit for, e.g. signalling or synchronisation, serial-parallel conversion being effected at the incoming junction circuits and parallelserial conversion at the outgoing junction circuits. Here also the checking is carried out by a pure comparison technique, equating waveforms from three similar units. Further, scanners are also provided for the central control of the system.

The scanners on the scanner cards referred to above each broadcasts to every replaceable unit which it serves in m bit code, in the present case m=8, and this is broadcast to each of the replacement units for each of the levels. At each of these replaceable units there is a multiplexing logic circuit which serves to gate a waveform designated by the broadcast code to a signal check lead, which extends from the unit being checked, see Fig. 2.

In Fig. 2 the equipment shown to the right of the broken line is on the scanner card while to the left we show in highly simplified form the three equivalent equipments of a traffic unit The selection information enters Fig.

2 via the input IP, and comes from a pro gramzrable read only memory (PROM), from the xw of that PROM which is addressed to cause checking. As will be seen later the PROM rows are addressed one after the other so that addresses selected for use in checking are thereby generated. As will be seen, this selection information is partly sent in parallel to the units to be checked and partly to selection units CH1, CH2, CH3. Together these serve to select a particular wavelorm from each of rhe n levels of the traffic unit concerned so that these 3 wavefonns may be compared for a period of approximately 1 millisecond, one against the other.In each of these levels the broadcast address information goes to a waveform selection device WSU on each unit, at which the lead to which that information is to be sent and the electrical condition thereon is signalled over a signal check lead SCL to the appropriate unit CHI, CH2, CH3. From these units the waveforms are applied to the Comparison checking unit CCU, and the results of the comparison are sent over the output connection shown to storage for subsequent use.

Thus the code broadcast can cause the condition of one of up to 256 sources to be directed to a scan card from each of the rep licated replaceable units. The waveforms pre sent at these sources are sampled at the basic clock rate of the logic circuitry before being checked by comparison, such that the minor dispersions in timing between the levels have no effect. At the beginning and end of every waveform check period of 1 millisecond a small "dead" period is included in which error detection is inhibited, which allows for the change in clock signal time to occur without any false error indication being given.

In using the comparison techniques described above much use is made of the data flow through the logic circuitry, and to realise its iull diagnostic power the check points are scanned in a sequence determined on the basis of the normal flow of data through the circuitry. In one case, see Fig. 3, which only shows one logic level, a functional logic block is divided into sections of related logic or chains, in each of which data flow starts at the beginning and continues in order. In Fig.

3 the logic is partitioned physically over three cards, and is in a number of chains, e.g.

A-F, B-E-H, B-H etc. I he scanning points are the outputs of the cards which are scanned in order through the chains, each chain being dealt with separately, so that the diagnostic power is high. In the case of chain A-C-F, all of the outputs of card 1 which relate to the chain are scanned, then those of card 2, and then those of card 3. If there are no faults in blocks A, C, F, the outputs at each point agree and the chain is passed as clear of faults. However, if there is a fault in card 1, i.e. block A, the effect of the fault propagates through C and F to cause apparent faults at their outputs. By scanning in the above order, the fault at A is detected and fault reports from subsequent links of the chains can be ignored. Thus the fault is located. As before, scans are at 1 milisec intervals.

The method of interconnection between the units of the system puts a limitation on the diagnostics in that connections made by multidriver/multi-receiver units do not allow location of a fault to a single replaceable unit but to the units as connected.

By using a PROM to store the test words which, as described above, select the check points, and stepping from test word to test word under the control of a counter, Fig.

4, it is possible to determine the details of the first failure in a chain in which failure has occurred, and to report each such failure to a central scan unit which forwards the error reports to the controlling processor for analysis, Fig. 5.

Each test word embodies the card address and the multiplex selection on the card, the chain number, a bit to indicate the start of a chain test, a bit to indicate the end of a chain test, and other bits to enable self-checking of the scan unit.

Reverting to Fig. 4, the results of corn- parisons are passed to two output registers from which they are sent to the central scan unit. If the output registers contain an indication (a) that either a fault has been detected, or (b) that a complete scan has been made without detection of an error and a scan complete message has been placed in the output register, then when a local scan unit receives a counter pulse from the central scan unit, the contents of the output registers are read out to the central scan unit. The information from the output register No. 1 is the inverse of that from No. 2, but in normal operation has the same meaning.If the central scan unit receives no message of type (a) or (b) within a pre-set period, e.g. 2 secs. then it "knows" that a malfunction has occurred and generates an error message for despatch to the controlling processor.

For a fault which has been detected in a scan period, each output register contains: (a) a bit indicating normal fault.

(b) the chain number.

(c) the levels on which the fault (assuming a normal fault) has been determined, i.e.

whether level 1 = level 2, level 2 = level 3, level 3 = level 1.

(d) the card number.

(e) the mux selection number.

Q a bit which is set if an inconsistency has been found in the scan itself, i.e. the self-checks for any local scan indicate malfunction.

Once a fault is registered in a series of checks on a chain, this fault indication is relayed to the central scan unit and no further faults during the remaining tests on this chain are recorded. The local scan is not allowed to proceed to check the next chain until the output registers have sent the fault information to the central unit and have been cleared.

When a test word is read out at the beginning of a test period of 1 millisecond (approx) and a bit in the test word indicates that this is the start of the check of a chain, then if the output registers are not clear the start of the test is delayed. In such case the test is not carried out during this period and the scan counter does not step on rhe next counter clock pulse from the central scan unit. A similar decision is made at the next dock pulse, 1 ms. later, as to whether to proceed with the test, and this is repeated until the output register tests clear, in which cdse the test proceeds.

The central scan unit may receive a set of result words from the local scan unit, and occasionally from more than one of the local scan units as a result of a malfunction. These error messages are stored in fault registers in the central scan unit. Normally this area of storage contains no fault information, a "fault detected" bistable is in its reset state, and all scan inputs are being considered by the central scan unit. If a fault is detected, it could be due to a transient, so during this scan period the "fault detected" bistable is set but the fault reports are ignored until the end of the current scan. Then a further bistable, the "fault detection primed" bistable for that local scan unit is set and remains set for a preset number of scan periods or until the controlling processor needs it.If in that preset number of scan periods a fault report is not received (or generated) by the central scan unit, the original fault report is assumed to be due to a transient and the bistables are reset. If a fault report Is thus received, that fault report and all subsequent ones are recorded up to the capacity of the storage or up to the end of the scan period.

Then a "fault confirmed" bistable is set and the controlling processor is interrupted.

No more fault reports are stored until the processor has serviced the interrupt, accepted the fault reports, cleared the fault storage area, and cleared the above-mentioned bistabies.

The equipment has facilities for masking fault reports from local scan units whose equipments are designated as receiving attention under the control of the processor. From the fault messages it has received, a diagnostic program in the processor causes a fault report to be originated.

The central scan unit which controls the cyclic scanning of the local scan units is itself triplicated, and supplies the necessary control waveforms to the local scan units (Fig. 4).

Most of the tests referred to above involve the comparison of replaceable unit outputs on three levels, but other checks on waveforms other than on outputs are made.

If the inputs to a chain are received from logic circuitry served by another local scan unit, the scan unit concerned cannot access the output waveforms at the distant local scan unit's location. In this case first tests are done on the inputs to the unit served to enable the processor's diagnostic programs to dis criminate between faults in the local unit and in the distant unit. Such checks are done in the normal sequencing of the chain. Thus in the example shown in Fig. 6, where MJD are majority decision devices, points such as X are tested in this manner, while points Z are considered as additional checks to deter mine whether any other detectable dormant faults exist. To facilitate such checking, one of the chain numbers is used for all such checks.

The concept underlying this invention has been described as applied to a digital switch, but the fundamental technique of selected comparative scanning can be used otherwise.

Thus it would be usable in a message trans mission sub-system (MTS), used for handling signalling traffic between the various switching centres of a large telecommunications network.

In such case local multiplexing is used, with control by a ROM, and checking is in the main done on the outputs of replaceable units.

We have indicated above that it is not always possible to locate a malfunction to the actual replaceable unit which is faulty, and in this respect Figs. 7 and 8 should be referred to. In such cases some indeterminacy may result and the fault only located to within (or between) a number of units, since it is not always possible in the course of the checks described to distinguish whether a sender, or a receiver or the interconnection is at fault.

However, the fault is nearly always located to the level.

For waveforms at the points X and V, Fig.

6, indeterminacy may arise as regards the level of a fault, but this is limited and isolated, and precautions can be taken as regards maintenance procedures.

Due to the flow of information through the logic, in certain cases it is only possible to locate the defective unit to within a small set of replaceable units within a level.

The local scanner contains an element of duplication and self checking, so that the central scan logic may ascertain to a high degree of probability the correct functioning of the local scan units.

WHAT WE CLAIM IS: 1. An electronic data handling system in which data handling units are replicated, there being n of each said unit (n > 3) working in parallel on the same data, in which the outputs of all of said n units at each stage of the system are compared and the output of the stage derived on the basis of a majority voting technique, in which for test purposes the units are sequentially selected with the selection process in respect of each said unit to be tested involving the stimulation of the said unit to perform a defined operation, and in which the results of the operations thus initiated for test purposes from all of the replicated units are checked so that if a fault occurs its location can be determined.

2. A system as claimed in claim 1, and in which the selection of said units for testing is effected under the control of a test selection programme held in a read-only memory.

3. A system as claimed in claim 2, in which the n units at each said stage are served by a scanner which, under control of address signals from said read-only memory, selects the units to be tested, in which each said unit has gating means adapted in response to its selection by a said scanner to gate a waveform appropriate to the selection code from said scanner to a checking lead, and in which the n checking leads for a said rounit stage go to a check circuit which identifies a faulty unit from information it receives over a said check lead 4.A system as ciarniea m claim I, 2, or 3, in which at each stage of the system there are a plurality of logic circuits with the logic circuits interconnected in chains each of which extends through a plurality of the system's stages and each of which chains is replicated, and in which to check a said chain the out puts of the units thereof are checked one after the other in the same order as that wherein data negotiates said circuit units.

5. A system as claimed in claim 4, in which the result of the--checking operations for each said stage are assembled in output registers associated with each said stage from which they are sent to a central control unit, and in which when all such information for one of said chain has been thus sent, the system advances to check the next one of said chains.

6. A system as claimed in claim 5 in which when a fault has been detected a first bistable is set to record said detection, in which if the fault condition is still present a preset period after the seting of the first bistable a second bistable is set, and in which a fault condition is only accepted as valid if both said bistables are set, whereby a transient-fault is ignored.

7. A system as claimed in any one of the preceding claims, in which the data handling system is an automatic telecommunications exchange system.

8. A data handling system substantially

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. logic circuitry served by another local scan unit, the scan unit concerned cannot access the output waveforms at the distant local scan unit's location. In this case first tests are done on the inputs to the unit served to enable the processor's diagnostic programs to dis criminate between faults in the local unit and in the distant unit. Such checks are done in the normal sequencing of the chain. Thus in the example shown in Fig. 6, where MJD are majority decision devices, points such as X are tested in this manner, while points Z are considered as additional checks to deter mine whether any other detectable dormant faults exist. To facilitate such checking, one of the chain numbers is used for all such checks. The concept underlying this invention has been described as applied to a digital switch, but the fundamental technique of selected comparative scanning can be used otherwise. Thus it would be usable in a message trans mission sub-system (MTS), used for handling signalling traffic between the various switching centres of a large telecommunications network. In such case local multiplexing is used, with control by a ROM, and checking is in the main done on the outputs of replaceable units. We have indicated above that it is not always possible to locate a malfunction to the actual replaceable unit which is faulty, and in this respect Figs. 7 and 8 should be referred to. In such cases some indeterminacy may result and the fault only located to within (or between) a number of units, since it is not always possible in the course of the checks described to distinguish whether a sender, or a receiver or the interconnection is at fault. However, the fault is nearly always located to the level. For waveforms at the points X and V, Fig. 6, indeterminacy may arise as regards the level of a fault, but this is limited and isolated, and precautions can be taken as regards maintenance procedures. Due to the flow of information through the logic, in certain cases it is only possible to locate the defective unit to within a small set of replaceable units within a level. The local scanner contains an element of duplication and self checking, so that the central scan logic may ascertain to a high degree of probability the correct functioning of the local scan units. WHAT WE CLAIM IS:

1. An electronic data handling system in which data handling units are replicated, there being n of each said unit (n > 3) working in parallel on the same data, in which the outputs of all of said n units at each stage of the system are compared and the output of the stage derived on the basis of a majority voting technique, in which for test purposes the units are sequentially selected with the selection process in respect of each said unit to be tested involving the stimulation of the said unit to perform a defined operation, and in which the results of the operations thus initiated for test purposes from all of the replicated units are checked so that if a fault occurs its location can be determined.

2. A system as claimed in claim 1, and in which the selection of said units for testing is effected under the control of a test selection programme held in a read-only memory.

3. A system as claimed in claim 2, in which the n units at each said stage are served by a scanner which, under control of address signals from said read-only memory, selects the units to be tested, in which each said unit has gating means adapted in response to its selection by a said scanner to gate a waveform appropriate to the selection code from said scanner to a checking lead, and in which the n checking leads for a said rounit stage go to a check circuit which identifies a faulty unit from information it receives over a said check lead

4.A system as ciarniea m claim I, 2, or 3, in which at each stage of the system there are a plurality of logic circuits with the logic circuits interconnected in chains each of which extends through a plurality of the system's stages and each of which chains is replicated, and in which to check a said chain the out puts of the units thereof are checked one after the other in the same order as that wherein data negotiates said circuit units.

5. A system as claimed in claim 4, in which the result of the--checking operations for each said stage are assembled in output registers associated with each said stage from which they are sent to a central control unit, and in which when all such information for one of said chain has been thus sent, the system advances to check the next one of said chains.

6. A system as claimed in claim 5 in which when a fault has been detected a first bistable is set to record said detection, in which if the fault condition is still present a preset period after the seting of the first bistable a second bistable is set, and in which a fault condition is only accepted as valid if both said bistables are set, whereby a transient-fault is ignored.

7. A system as claimed in any one of the preceding claims, in which the data handling system is an automatic telecommunications exchange system.

8. A data handling system substantially

as described with reference to the drawings accompanying drawings the Provisional Specification.