JPH0520020B2 - - Google Patents

Info

Publication number
JPH0520020B2
JPH0520020B2 JP59262716A JP26271684A JPH0520020B2 JP H0520020 B2 JPH0520020 B2 JP H0520020B2 JP 59262716 A JP59262716 A JP 59262716A JP 26271684 A JP26271684 A JP 26271684A JP H0520020 B2 JPH0520020 B2 JP H0520020B2
Authority
JP
Japan
Prior art keywords
communication path
signal
channel
upstream
downstream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59262716A
Other languages
Japanese (ja)
Other versions
JPS61141246A (en
Inventor
Masataka Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26271684A priority Critical patent/JPS61141246A/en
Publication of JPS61141246A publication Critical patent/JPS61141246A/en
Publication of JPH0520020B2 publication Critical patent/JPH0520020B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/24Arrangements for supervision, monitoring or testing with provision for checking the normal operation
    • H04M3/244Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は時分割電子交換機の通話路導通試験方
法に係り、特に通話路装置の障害切り分けに好適
な通話路導通試験方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a communication line continuity test method for a time-division electronic exchange, and particularly to a communication line continuity test method suitable for isolating faults in communication line equipment.

〔発明の背景〕[Background of the invention]

従来の通話路導通試験方法を第3図を参照して
説明する。
A conventional communication line continuity test method will be explained with reference to FIG.

第3図には2つの通話路装置A,Bが示されて
おり、各通話路装置A,Bは、夫々上り側通話路
装置AU,BU及び下り側通話路装置AD,BDで構成
されている。そして、端末装置甲から送出された
データ信号は、上り側通話路装置AU,BU及び下
り側通話路装置BD,ADを通つて、端末装置乙に
伝送されるようになつている。また、従来の各通
話路装置A,Bは、夫々装置内に通話路折り返し
機能を備えており、パターンジエネレータPGか
らの試験番号を通話路装置B内にて折り返し、ま
た通話路装置A内にて折り返し、折り返した試験
信号をパターンチエツカーPCで検査するように
なつている。尚、符号1及び2は夫々位相合せ回
路及びセレクタを示している。
In FIG. 3, two channel devices A and B are shown, and each channel device A, B is composed of an upstream channel device A U , B U and a downstream channel device A D , B D , respectively. It is made up of. The data signal sent from the terminal device A is transmitted to the terminal device B through the upstream channel devices A U and BU and the downstream channel devices B D and AD . . In addition, each of the conventional communication path devices A and B has a call path return function within the device, and the test number from the pattern generator PG is looped back within the communication path device B, and also within the communication path device A. The pattern checker PC returns the returned test signal. Note that numerals 1 and 2 indicate a phase matching circuit and a selector, respectively.

この従来の試験方法では、通話路装置内に設け
たシフトレジスタやメモリ等で構成した折り返し
機構により試験信号を折り返す為、ハード量が大
きくなるという欠点を持つ。更に、例えばB装置
内にて折り返し導通試験を行なつて“OK”とな
り、A装置内にて折り返し導通試験を行なつて
“NG”となつた場合でも、100%の確立で障害が
A装置内に生じていると判断できないという不具
合がある。つまり、例えばB装置内の折り返し点
Pと、B装置から通話路に出る出力点Qとの間に
存在するハードに故障が生じていた場合には、こ
れを検出できない。
This conventional test method has the disadvantage that the amount of hardware is large because the test signal is returned by a return mechanism constituted by a shift register, memory, etc. provided in the communication path device. Furthermore, for example, even if a loop continuity test is performed in device B and the result is "OK," and a loop continuity test is performed in device A and the result is "NG," there is a 100% probability that the fault is in device A. There is a problem in that it cannot be determined that it is occurring internally. That is, for example, if a failure occurs in the hardware that exists between the return point P in the B device and the output point Q from the B device to the communication path, this cannot be detected.

このように、従来の試験方法は、ハード量が大
きく、しかも障害切り分けを完全にできないとい
う欠点を有していた。
As described above, conventional testing methods have the disadvantage that they require a large amount of hardware and cannot completely isolate faults.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ハード量を小さくし、しかも
完全な障害切り分けを可能とする通話路導通試験
方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a communication path continuity test method that reduces the amount of hardware and makes it possible to completely isolate faults.

〔発明の概要〕[Summary of the invention]

本発明では、通話路装置間の上り側通話路と下
り側通路を伝搬する夫々の信号のフレーム位相を
等しくし、下り側通路を伝搬する信号を上り側通
話路に折り返して該折り返し区間内に在る通話路
装置の導通試験を行なう。
In the present invention, the frame phases of the respective signals propagating on the uplink path and the downlink path between the communication path devices are made equal, and the signals propagating in the downlink path are looped back to the uplink path and within the folding section. Perform a continuity test on existing communication line equipment.

このように、通話路装置内に折り返し機能を設
ける必要がない為、その分のハード量が減少し、
通話路装置外において信号を折り返すようにした
ので、障害の切り分けが可能となる。
In this way, there is no need to provide a return function within the communication path device, so the amount of hardware is reduced accordingly.
Since the signal is looped back outside the communication path device, it becomes possible to isolate the fault.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図及び第2図を
参照して説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第1図は、本発明による通話路導通試験方法を
適用した通話路装置の一実施例の接続構成図であ
る。
FIG. 1 is a connection configuration diagram of an embodiment of a communication path device to which the communication path continuity testing method according to the present invention is applied.

通話路装置Aは、上り側通話路装置AUと下り
側通話路装置ADとで構成され、通話路装置Bは
上り側通話路装置BUと下り側通話路装置BDとで
構成されている。導通試験用の試験信号を発生す
るパターンジエネレータPGの出力信号は、下り
側通話路装置D、通話路10、下り側通話路装置
AD、通話路11、上り側通話路装置AU、通話路
12、上り側通話路装置BUを介してパターンチ
エツカPCに送出されるようになつている。また、
通話路10の途中から試験信号を折り返しこれを
上り側通話路装置BUに戻す通話路13を設けて
ある。上り側通話路装置BU内には、通話路12
または通話路13からの信号を切り換えてパター
ンチエツカPCに入力するセレクタイ2を設けて
ある。
The channel device A is composed of an upstream channel device A U and a downstream channel device A D , and the channel device B is composed of an upstream channel device B U and a downstream channel device B D. ing. The output signal of the pattern generator PG that generates the test signal for the continuity test is transmitted to the downstream channel device D , the channel 10, and the downstream channel device.
The data is sent to the pattern checker PC via A D , the communication path 11, the upstream communication path device AU , the communication path 12, and the upstream communication path device BU . Also,
A communication path 13 is provided for returning the test signal from the middle of the communication path 10 and returning it to the upstream communication path device BU . In the upstream communication path device B U , there is a communication path 12.
Alternatively, a selector 2 is provided for switching the signal from the communication path 13 and inputting the signal to the pattern checker PC.

上り側通話路装置AU,BUの図示しない装置間
インターフエースと、下り側通話路装置AD,BD
の図示しない装置のインターフエースにより、各
装置間の通話路10,12を伝搬する信号のフレ
ーム位相を、例えば第2図に示すように等しくし
ておく。
Inter-device interface (not shown) of upstream communication path devices A U and B U and downstream communication path devices A D and B D
The frame phases of the signals propagating through the communication paths 10 and 12 between the respective devices are made equal, for example, as shown in FIG. 2, by an interface of a device (not shown).

第2図に示した信号(通話路データ)は、1フ
レームを32タイムスロツトで構成し、各タイムス
ロツトは夫々8ビツトで構成してある。そして、
上り側通話路装置AU−BU間の通話路データのタ
イムスロツトゼロ(TS0)における先頭のビツト
0の位置と、下り側通話路装置BD−AD間の通話
路データのタイムスロツトゼロ(TS0)における
先頭のビツト0の位置とを等しくしてある。この
よに、フレーム位相を等しくすることは、時分割
方式を採用する電子交換機にあつては、容易に行
なうことができる。
In the signal (communication path data) shown in FIG. 2, one frame consists of 32 time slots, and each time slot consists of 8 bits. and,
The position of the first bit 0 at time slot zero (TS0) of the communication path data between the upstream communication path devices A U and B U and the time slot zero of the communication path data between the downstream communication path devices B D and A D. The position of the first bit 0 in (TS0) is made equal. In this way, making the frame phases equal can be easily achieved in an electronic exchange that employs a time division system.

障害が発生して通話路装置Aと通話路装置Bの
障害切り分けを行なう必要がある場合、フレーム
信号(第2図)に同期してセレクタ2を切り換
え、パターンジエネレータPGからの試験信号を
特定のタイムスロツトのみ折り返し、PG→BD
BU→PCのルートで導通試験を行なう。通話路装
置Aからの上り側通話路データと、通話路装置B
からの下り側通話路データのどちらの位相も等し
いため、セレクタ2による切り換えが可能とな
り、その結果が“OK”の場合には、通話路装置
Aの通話路障害であると判断できる。導通試験結
果が“NG”の場合は、通話路装置Bが障害であ
ると判断でき、この通話路装置Bを交換後に通話
路障害が起これば、前記通話路装置Aも障害であ
つたと判断できる。
When a fault occurs and it is necessary to isolate the fault between channel device A and channel device B, selector 2 is switched in synchronization with the frame signal (Figure 2) to identify the test signal from pattern generator PG. Only the time slot of PG → B D
Perform a continuity test on the route B U → PC. Uplink channel data from channel device A and channel device B
Since both phases of the downstream communication path data from the communication path device A are equal, switching by the selector 2 is possible, and if the result is "OK", it can be determined that there is a communication path failure in the communication path device A. If the continuity test result is "NG", it can be determined that the communication path device B is at fault, and if a communication path failure occurs after this communication path device B is replaced, it is determined that the communication path device A is also at fault. can.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、障害発生時の通話路装置の掌
害切り分けが可能な為、時分割電子交換機の保守
性の向上を図れる。また、通話路装置内ではな
く、通話路装置間で折り返す為、ハードウエアの
部品が従来に比べて減少し、経済性も向上する。
According to the present invention, since it is possible to isolate the damage to the communication path device when a failure occurs, it is possible to improve the maintainability of the time division electronic exchange. In addition, since the loop is looped between the communication path devices rather than within the communication path device, the number of hardware parts is reduced compared to the conventional method, and economical efficiency is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による通話路導通試験方法を適
用した通話路装置の一実施例の接続構成図、第2
図は本発明方法の一実施例を説明する通話路デー
タの位相図、第3図は従来の通話路導通試験方法
を説明する通話路装置の接続構成図である。 AU,BU……上り側通話路装置、AD,BD……下
り側通話路装置、甲,乙……端末装置、PG……
パターンジエネレータ、PC……パターンチエツ
カ、1……位相合せ回路、2……セレクタ、1
0,11,12,13……通話路。
FIG. 1 is a connection configuration diagram of an embodiment of a communication path device to which the communication path continuity test method according to the present invention is applied;
FIG. 3 is a phase diagram of channel data for explaining an embodiment of the method of the present invention, and FIG. 3 is a connection configuration diagram of a channel device for explaining a conventional channel continuity testing method. A U , B U ... Uplink communication path equipment, A D , B D ... Downlink communication path equipment, Party A, Party B... Terminal equipment, PG...
Pattern generator, PC...Pattern checker, 1...Phase matching circuit, 2...Selector, 1
0, 11, 12, 13...Call path.

Claims (1)

【特許請求の範囲】[Claims] 1 時分割電子交換機において、第1、第2の上
り側通話路装置と、第1、第2の下り側通話路装
置と、上記第1の下り側通話路装置に結合され、
導通試験用の試験信号を発生する信号発生装置
と、該信号発生装置の信号を上記第1の下り側通
話路装置を介して上記第2の下り側通話路装置に
導く第1の通話路と、上記第2の下り側通話路装
置に導かれた上記第1の通話路の信号を上記第1
の上り側通話路装置に導く第2の通話路と、上記
第1の上り側通話路装置に導かれた上記第2の通
話路の信号を上記第2の上り側通話路装置に導く
第3の通話路と、上記第1の通話路の信号を上記
第2の上り側通話路装置に導く第4の通話路と、
上記第2の上り側通話路装置に設けられ、上記第
3及び上記第4の通話路の信号を受けて、該第4
の通話路の信号をセレクトするセルクタと、該セ
レクタにてセレクトさた信号をチエツクする装置
に導く手段とを具え、上記第1の通話路と上記第
3の通話路の信号のフレーム位相を等しくし、上
記第1の通話路の信号を上記セレクタを介して上
記チエツク装置に折り返し、該折り返し区間内に
在る通話路の試験を行うことを特徴とする通話路
導通試験方法。
1 in a time division electronic exchange, first and second uplink channel devices, first and second downlink channel devices, and coupled to the first downlink channel device;
a signal generating device that generates a test signal for a continuity test; a first channel that guides the signal of the signal generating device to the second downstream channel device via the first downstream channel device; , the signal on the first communication path guided to the second downstream communication path device is transmitted to the first communication path device.
a second communication path leading to the upstream communication path device; and a third channel guiding the signal of the second communication path guided to the first upstream communication path device to the second upstream communication path device. a fourth communication path that guides the signal of the first communication path to the second upstream communication path device;
provided in the second upstream communication path device, receiving signals from the third and fourth communication paths;
a cell selector for selecting a signal on a communication path; and means for guiding the signal selected by the selector to a checking device; A communication path continuity testing method characterized in that the signal on the first communication path is returned to the check device via the selector, and the communication path existing within the return section is tested.
JP26271684A 1984-12-14 1984-12-14 Channel continuity test method Granted JPS61141246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26271684A JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26271684A JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Publications (2)

Publication Number Publication Date
JPS61141246A JPS61141246A (en) 1986-06-28
JPH0520020B2 true JPH0520020B2 (en) 1993-03-18

Family

ID=17379599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26271684A Granted JPS61141246A (en) 1984-12-14 1984-12-14 Channel continuity test method

Country Status (1)

Country Link
JP (1) JPS61141246A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758491A (en) * 1980-09-26 1982-04-08 Nec Corp Channel continuity test system for digital exchanger

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758491A (en) * 1980-09-26 1982-04-08 Nec Corp Channel continuity test system for digital exchanger

Also Published As

Publication number Publication date
JPS61141246A (en) 1986-06-28

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