JPH03229175A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To test a circuit with high efficiency temporally and economically by inputting an output signal from the same function block in an exclusive OR gate at the time of performing a test and detecting whether each block outputs the same signal based on the output from the exclusive OR gate. CONSTITUTION:When a semiconductor integrated circuit performs an ordinary action, a test signal is set at L. When the respective blocks 1 and 2 ordinarily acts, the signals outputted to an OUT1i and OUT2i are same, so that the signal of the OUT1i and the signal of the OUT2i are outputted to an OUT1 and an OUT2 respectively. Since the respective output signals are outputted to the outside through the exclusive OR gates (a) and (b), skew is not caused by consti tuting exclusive OR by the same kind of device. At the time of performing the test, the test signal is set at H. In a state where CS1 and CS2 are set at the H and the blocks 1 and 2 are made to act, a test pattern is impressed on an IN. When the respective blocks normally act, the same signal is outputted to the OUT1i and the OUT2i and the L is always outuptted to the OUT1. In the case that the respective blocks do not act normally, the H is outputted to the OUT1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit for a semiconductor integrated circuit having a plurality of identical functional blocks.

[Conventional technology]

FIG. 2 is a block diagram of a conventional semiconductor integrated circuit having a plurality of identical functional blocks. Note that the figure shows a case where the number of blocks is two. In the figure, ■ and 2 are the same functional blocks, and C31 and CS2 are the same functional blocks!
, a chip select signal terminal for enabling operation of 2;
IN indicates a group of human input signal terminals for each of the same functional blocks 1.2, and 0UTI and 0UT2 indicate output signal terminals of each of the same functional blocks 1.2.

Next, the operation will be explained. There are two methods for testing this semiconductor integrated circuit.

The first method is to set C5I and C32 to H.
gh, and the signal is High active. Further, L indicates Low. (Similar symbols will be used below)
, with both blocks 1 and 2 enabled, apply a test pattern to IN. At this time 0UT1
．． Since signals are output to both output terminals of 0UT2, a tester comparator (not shown) is used to determine whether the output signals are correct.
Connect. Therefore, this entire semiconductor integrated circuit requires as many comparators as the total number of output terminals of block 1 and block 2.

The second method is to set C3I to H and CS2 to block 1.
A test pattern is applied to IN in a state where only 1 is enabled. At this time, since a signal is output only to OUT 1, the number of comparators in the tester is equal to the number of output terminals of the block 1 terminals. After testing block 1, set CS2 to H and C31 to L to test block 2. Therefore, testing the entire semiconductor integrated circuit requires twice as much time as testing a single block.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuits with multiple identical functional blocks were configured as described above, so testing the same blocks individually would take time, and testing all blocks at the same time would require a large number of tester comparators. There was a problem that it was necessary and uneconomical in terms of time and money.

This invention was made in order to solve the above problems, and it is a semiconductor integrated circuit that can test all blocks with the test time required to test a single block and the number of comparators in the tester. The purpose is to obtain.

(Means for Solving the Problems) A semiconductor integrated circuit according to the present invention includes an exclusive OR gate that detects that the output signals of the same functional blocks are the same during testing, and a test signal that is input during testing. There is a skew between the test signal terminal, the AND gate for generating a signal to control the exclusive OR gate by the test signal manually input from this test signal terminal, and the output signal of each same functional block during normal operation. In order to prevent this from occurring, an exclusive OR gate is provided which is connected to the output of each functional block.

[Effect]

In the semiconductor integrated circuit according to the present invention, during testing, the output signals of each of the same functional blocks are input to the exclusive OR gate, it is detected from the output whether each block is outputting the same signal, and the exclusive OR gate is operated. The output signal is output to the output terminal of one block, so all blocks are tested simultaneously, and the number of output terminals is the same as the number of terminals of one block, so the number of comparators in the tester is one. All you need is the number of blocks. Furthermore, during normal operation, no skew occurs between the outputs of the same functional blocks due to the exclusive OR gates connected to the outputs of the same functional blocks.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a semiconductor integrated circuit including a plurality of identical functional blocks, which is an embodiment of the present invention. Note that the figure shows a case where the number of blocks is two. In the figure, a,
b is exclusive OR gate, C is AND gate, TEST
0UT1i and 0UT2i indicate one of the output signals of each of the same functional blocks. In addition, other symbols indicate the same ones as in the conventional navigation system. In addition, each functional block 1
．． All of the output signals outputted from 2 are connected to an external output terminal via a test circuit composed of logic gates as shown in the figure, but this is not shown in the figure.

Next, the operation will be explained. Table 1 is a truth table for the test circuit in FIG.

Table 1 When this semiconductor integrated circuit operates normally, the test signal is set to L. If each block 1.2 operates normally, the signals output to 0UTI i and 0UT2i are the same, so from Table 1, the 0UT1i signal is output to 0UTI, or the 0UT2i signal is output to 0UT2. .

Since each output signal is output to the outside via one exclusive OR gate a, b, skew will not occur if the exclusive OR is configured with the same type of devices.

When testing, set the test signal to H.

CSI and C32 are set to H, and a test pattern is applied to IN with blocks 1 and 2 enabled.

When each block operates normally, 0UT1i and 0UT2
The same signal is output to i, so from Table 1, 0UTI
will always be output. Also, if each block does not operate normally and outputs different signals, 0U
H is output to TI. Therefore, OUT 1 (3
By testing only the issue, it is possible to test the entire block. Moreover, the test time is only required to test a single block.

(Effects of the Invention) As described above, according to the present invention, a semiconductor integrated circuit having a plurality of identical functional blocks can be tested extremely efficiently in terms of time and economy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit having a plurality of identical functional blocks, which is an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor integrated circuit having a plurality of identical functional blocks. In the figure, 1 and 2 are the same functional blocks, a and b are exclusive OR gates, C is an AND gate, and TEST is a test signal terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a semiconductor integrated circuit having a plurality of identical functional blocks, an exclusive OR gate detects that the output signals of the identical functional blocks are the same during testing, and a test signal terminal to which a test signal is input during testing. and an AND gate for generating a signal for controlling the exclusive OR gate according to the test signal input from the test signal terminal, and generating a skew between the output signals of each of the same functional blocks during normal operation. 1. A semiconductor integrated circuit comprising an exclusive OR gate connected to the output of each identical functional block to prevent