JPS61140155A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61140155A JPS61140155A JP26074684A JP26074684A JPS61140155A JP S61140155 A JPS61140155 A JP S61140155A JP 26074684 A JP26074684 A JP 26074684A JP 26074684 A JP26074684 A JP 26074684A JP S61140155 A JPS61140155 A JP S61140155A
- Authority
- JP
- Japan
- Prior art keywords
- mechanical strength
- nitride film
- moisture resistance
- memory cell
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
[技術分野]
本発明は、ワンチップ上に占めるEPROMの面積が小
さい半導体装置に適用して有効な技術に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor device in which an EPROM occupies a small area on one chip.
[背景技術]
一般に、半導体基板(いわゆる半導体チップ)の表面は
、耐湿性および機械的強度に優れた表面保護膜によって
被われている。この表面保護膜はファイナル・パッシベ
ーション膜といわれるもので、プラスチックやセラミッ
クによるパッケージと相俟って半導体チップを外部環境
から保護する重要な機能をもつ。耐湿性および機械的強
度の点からすると、プラズマCVD法によるシリコンナ
イトライド膜(以下、プラズマ・ナイトライド膜という
)が、表面保護膜として最適である。[Background Art] Generally, the surface of a semiconductor substrate (so-called semiconductor chip) is covered with a surface protective film having excellent moisture resistance and mechanical strength. This surface protection film is called a final passivation film, and together with the plastic or ceramic package, it has an important function of protecting the semiconductor chip from the external environment. From the viewpoint of moisture resistance and mechanical strength, a silicon nitride film produced by plasma CVD (hereinafter referred to as a plasma nitride film) is most suitable as a surface protective film.
しかし、プラズマ・ナイトライド膜は紫外線の透過性に
劣るため、紫外線消去型のEPROMにあっては、記憶
内容を消去する消去特性が悪くなるという問題がある。However, since the plasma nitride film has poor transmittance to ultraviolet rays, there is a problem in the ultraviolet erasable EPROM in that the erasing characteristics for erasing the stored contents are deteriorated.
そこで、紫外線消去型のEPROM用表面保護膜として
、耐湿性と紫外線透過性を兼ね備えた酸化窒化膜(ox
ynitrids)を用いるという試みがなされている
。Therefore, as a surface protection film for UV-erasable EPROMs, an oxynitride film (OX
Attempts have been made to use ynitrids.
ところが、その酸化窒化膜においては、機械的強度の点
に難点があり、保護膜を2層構造にするなどの工夫をな
さざるをえないようである(以上。However, the oxynitride film has a drawback in terms of mechanical strength, and it seems that it is necessary to take measures such as making the protective film a two-layer structure (as described above).
日経エレクトロニクス、1984年5月7日号、ρ16
1参照)。Nikkei Electronics, May 7, 1984 issue, ρ16
(see 1).
[発明の目的コ
本発明の目的は、EPROM内蔵マイコンのようにワン
チップ上にCPUや入出力装置などとともに紫外線消去
型のEPROMを有する半導体装置において、耐湿性お
よび機械的強度を保ち、しかも消去特性の点でも問題の
ないチップ表面保護技術を提供することにある。[Objective of the Invention] The object of the present invention is to maintain moisture resistance and mechanical strength, and to erase data in a semiconductor device such as a microcomputer with built-in EPROM, which has an ultraviolet erasable EPROM along with a CPU, input/output device, etc. on a single chip. The object of the present invention is to provide a chip surface protection technology that has no problems in terms of characteristics.
本発明の前記ならびにその他の目的と新規な特徴は、本
明J!書の記述および添付図面から明らかになるであろ
う。The above and other objects and novel features of the present invention are accomplished by the present invention J! It will become clear from the description in the book and the attached drawings.
[発明の概要コ
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.
すなわち、半導体チップ上、EPROMのメモリセル部
分のみを紫外線透過性の良好な酸化窒化膜で被うのに対
し、他の部分を耐湿性および機械的強度のきわめて良好
なプラズマ・ナイトライド膜で被うようにし、チップ全
体としての耐湿性、機械的強度を維持しつつ消去特性の
向上を図るようにしている。In other words, only the memory cell portion of the EPROM on the semiconductor chip is covered with an oxynitride film that has good UV transparency, while the other parts are covered with a plasma nitride film that has extremely good moisture resistance and mechanical strength. In this way, the erase characteristics are improved while maintaining the moisture resistance and mechanical strength of the chip as a whole.
[実施例]
第1@は本発明による半導体装置の一実施例のチップ平
面図、第2図は第1図のn−n線に沿った断面図である
。Embodiment 1 is a chip plan view of an embodiment of the semiconductor device according to the present invention, and FIG. 2 is a sectional view taken along line nn in FIG. 1.
シリコン基板から成る半導体基板1には1図示しないが
、EPROMやCPUなどが形成されており、それ自体
がワンチップマイクロコンピュータとしての機能を備え
ているにのような半導体基板1上、EPROMメモリセ
ル部分2以外の部分3を、耐湿性および機械的強度の良
好なプラズマ・ナイトライド膜4で被い、メモリセル部
分2については紫外線透過性の良好な酸化窒化膜5で被
っている。第1図および第2図に示す例の場合、プラズ
マ・ナイトライド膜4をパターニングした後、酸化窒化
膜5を形成しているが、第3図に示すように、酸化窒化
膜5を形成してからプラズマ・ナイトライド膜4を形成
したり、あるいは、第4図に示すように、酸化窒化膜5
については、半導体基板1の全面を被うようにすること
もできる。Although not shown in the figure, a semiconductor substrate 1 made of a silicon substrate has an EPROM, a CPU, etc. formed thereon, and has an EPROM memory cell, which itself has the function of a one-chip microcomputer. The portion 3 other than the portion 2 is covered with a plasma nitride film 4 having good moisture resistance and mechanical strength, and the memory cell portion 2 is covered with an oxynitride film 5 having good ultraviolet transmittance. In the example shown in FIGS. 1 and 2, the oxynitride film 5 is formed after patterning the plasma nitride film 4, but as shown in FIG. 3, the oxynitride film 5 is formed. After that, a plasma nitride film 4 is formed, or as shown in FIG. 4, an oxynitride film 5 is formed.
In this case, it is also possible to cover the entire surface of the semiconductor substrate 1.
EPROM内蔵マイコンテは、EPROMメモリセル部
分2の占める面積はごくわずかである。In a microcomputer with built-in EPROM, the area occupied by the EPROM memory cell portion 2 is very small.
そこで、メモリセル部分2の上を被う酸化窒化膜5が機
械的強度の点で若干難点はあるものの、半導体基板1の
表面のほとんどは耐湿性および機械的強度のきわめて良
好なプラズマ・ナイトライド膜4で被われているので、
チップ全体から見ると。Therefore, although the oxynitride film 5 covering the memory cell portion 2 has some drawbacks in terms of mechanical strength, most of the surface of the semiconductor substrate 1 is made of plasma nitride, which has extremely good moisture resistance and mechanical strength. Since it is covered with membrane 4,
Looking at the whole chip.
耐湿性および機械的強度に優れ、かつ消去特性の点の問
題も解消されることになる。It has excellent moisture resistance and mechanical strength, and also solves the problem of erasing properties.
[効果コ
チップ上、EPROMのメモリセル部分のみを紫外線透
過性の良好な膜で選択的に被い、他の部分を耐湿性およ
び機械的強度の良好な膜で被っているので、チップ全体
としての表面保護機能を維持しつつ消去特性の向上を図
ることができる。[Effects] On the chip, only the memory cell portion of the EPROM is selectively covered with a film that has good ultraviolet transparency, and the other parts are covered with a film that has good moisture resistance and mechanical strength, so that the overall chip Erasing characteristics can be improved while maintaining the surface protection function.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもなし1゜
[利用分野]
本発明は、紫外線消去型のEPROMを一部に含む半導
体装置に広範に適用することができるが、特に、EPR
OMメモリセル面積の占有率が低いものに適用するほど
より大きな実効を得ることができる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. 1゜[Field of Application] The present invention can be widely applied to semiconductor devices that partially include ultraviolet erasable EPROM, but is particularly applicable to EPR
The lower the OM memory cell area occupation rate, the greater the effect can be obtained.
第1図は本発明の一実施例を示す平面図、第2図は第1
図の■−■線に沿った断面図、第3図および第4図はそ
れぞれ他の実施例を示す断面図である。Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing an embodiment of the present invention.
A cross-sectional view taken along the line ■--■ in the figure, and FIGS. 3 and 4 are cross-sectional views showing other embodiments, respectively.
Claims (1)
線消去型のEPROMを有する半導体装置において、前
記EPROMのメモリセル部分を被う表面保護膜として
、他の部分を被う表面保護膜よりも紫外線の透過性の良
い膜を用いたことを特徴とする半導体装置。1. In a semiconductor device having an ultraviolet-erasable EPROM together with other functional elements on one semiconductor substrate, the surface protective film covering the memory cell portion of the EPROM is more suitable than the surface protective film covering other parts. A semiconductor device characterized by using a film that is highly transparent to ultraviolet rays.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26074684A JPS61140155A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26074684A JPS61140155A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61140155A true JPS61140155A (en) | 1986-06-27 |
Family
ID=17352165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26074684A Pending JPS61140155A (en) | 1984-12-12 | 1984-12-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61140155A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63269554A (en) * | 1987-04-27 | 1988-11-07 | Mitsubishi Electric Corp | Semiconductor device |
WO2014129252A1 (en) * | 2013-02-21 | 2014-08-28 | セイコーインスツル株式会社 | Ultraviolet-erasable nonvolatile semiconductor device |
-
1984
- 1984-12-12 JP JP26074684A patent/JPS61140155A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63269554A (en) * | 1987-04-27 | 1988-11-07 | Mitsubishi Electric Corp | Semiconductor device |
WO2014129252A1 (en) * | 2013-02-21 | 2014-08-28 | セイコーインスツル株式会社 | Ultraviolet-erasable nonvolatile semiconductor device |
JP2014165191A (en) * | 2013-02-21 | 2014-09-08 | Seiko Instruments Inc | Ultraviolet ray erasure type nonvolatile semiconductor device |
CN105074887A (en) * | 2013-02-21 | 2015-11-18 | 精工电子有限公司 | Ultraviolet-erasable nonvolatile semiconductor device |
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