KR960701475A - SINGLE POLYSILICON LAYER E²PROM CELL - Google Patents

SINGLE POLYSILICON LAYER E²PROM CELL Download PDF

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Publication number
KR960701475A
KR960701475A KR1019950703819A KR19950703819A KR960701475A KR 960701475 A KR960701475 A KR 960701475A KR 1019950703819 A KR1019950703819 A KR 1019950703819A KR 19950703819 A KR19950703819 A KR 19950703819A KR 960701475 A KR960701475 A KR 960701475A
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South Korea
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region
semiconductor type
gate oxide
cell
substrate
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KR1019950703819A
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Korean (ko)
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시. 왱 패트릭
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스티븐 에시. 라움
래티스 세미콘덕터 코퍼레이션
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Publication of KR960701475A publication Critical patent/KR960701475A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 메모리 셀, 특히 단일한 다결정실리콘 층만을 가지는 이이피롬(E2PROM)셀에 관한 것으로, 이 이이피롬 셀이 한 반도체 형인 기판과 그 기판의 표면에 형성된 다른 반도체 형인 소스 및 드레인 영역(210)(212)과 이 소스 및 드레인 사이에 형성된 채널 영역(216)을 구비하며 상기 채널 영역상에는 상대적으로 두꺼운 산화막층이 형성되고 상기 소스 및 드레인 영역상의 일부분에는 상대적으로 얇은 산화막층이 형성되며, 셀이 플로팅 게이트를 형성하는 오직 하나의 다결정실리콘 층을 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a memory cell, in particular an E 2 PROM cell having only a single polysilicon layer, wherein the source and drain regions of the substrate are one semiconductor type and other semiconductor types formed on the surface of the substrate. 210 and 212 and a channel region 216 formed between the source and the drain, wherein a relatively thick oxide layer is formed on the channel region, and a relatively thin oxide layer is formed on a portion of the source and drain region. The cell is characterized by including only one polysilicon layer forming a floating gate.

Description

단일한 다결정실리콘 층을 가진 이이피롬 셀(SINGLE POLYSILICON LAYER E2PROM CELL)SINGLE POLYSILICON LAYER E2PROM CELL with a single polycrystalline silicon layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 이이피롬 셀의 도면,3 is a diagram of an ipyrom cell according to the present invention;

제4도는 제3도의 선 4-4를 따라 절단한 것으로서 셀을 프로그래밍 하는 상태를 나타내는 단면도,4 is a cross-sectional view showing a state of programming a cell as cut along line 4-4 of FIG.

제5도는 제4도에서 셀을 지우기 하는 상태를 나타낸 단면도.5 is a cross-sectional view showing a state of erasing cells in FIG.

Claims (7)

기판의 표면을 따라서 놓이고 또한 기판 내부로 연장된 제2반도체 형인 제1 및 제2영역을 포함하는 제1반도체 형의 기판; 상기 기판 표면을 따라 사이에 채널을 형성하는 제2반도체 형인 제1 및 제2영역; 및 상기 채널 영역 및 제2반도체 형인 상기 제1영역과 제2영역의 일부분 상에 형성된 게이트 산화막을 구비하며; 상기 게이트 산화막은 상기 채널 영역상에 놓인 상대적으로 두꺼운 제1부분, 제2반도체 형인 상기 제1영역의 일부분상에 놓인 상대적으로 얇은 제2부분 및 제2반도체 형인 상기 제2영겨의 일부분상에 놓인 상대적으로 얇은 제3부분을 가지며, 상기 제2부분 및 제3부분이 같은 두께를 가지며, 상기 제1 및 제2부분을 연결하는 게이트 산화막 부분이 상기 채널 영역에 인접한 상기 제1반도체 형인 상기 제1영역의 가장자리와 거의 정렬되어 있고, 상기 제1 및 제3부분을 연결하는 게이트 산화막 부분이 상기 채널 영역에 인접한 상기 제2반도체 형인 상기 제2영역의 가장자리와 가의 정렬되어 있는 것을 특징으로 하는 이이피롬 셀.A first semiconductor type substrate comprising first and second regions of a second semiconductor type lying along a surface of the substrate and extending into the substrate; First and second regions of a second semiconductor type forming a channel therebetween along the substrate surface; And a gate oxide film formed on a portion of the first region and the second region, the channel region and the second semiconductor type; The gate oxide layer overlies a relatively thick first portion overlying the channel region, a relatively thin second portion overlying a portion of the first region that is of a second semiconductor type and a portion of the second fringe of the second semiconductor type. Said first portion having a relatively thin third portion, said second portion and said third portion having the same thickness, and wherein said gate oxide portion connecting said first and second portions is said first semiconductor type adjacent said channel region; Ipirom, characterized in that substantially aligned with the edge of the region, the gate oxide film portion connecting the first and the third portion is aligned with the edge of the second region of the second semiconductor type adjacent to the channel region. Cell. 제1항에 있어서, 상기 게이트 산화막 상에 형성되며 셀의 단일한 다결정실리콘 층의 일부가 되는 플로팅 게이트를 더 구비한 것을 특징으로 하는 이이피롬 셀.2. The ypyrom cell of claim 1, further comprising a floating gate formed on the gate oxide and becoming part of a single polysilicon layer of the cell. 제1항에 있어서, 상기 상대적으로 두꺼운 부분, 상기 상대적으로 얇은 부분 및 상기 제1 및 제2부분을 연결하는 게이트 산화막이 함께 단차를 이루는 것을 특징으로 하는 이이피롬 셀.2. The ypyrom cell according to claim 1, wherein the relatively thick portion, the relatively thin portion, and the gate oxide layer connecting the first and second portions form a step together. 기판의 표면을 따라서 놓이고 또한 기판 내부로 연장된 제2반도체 형인 제1 및 제2영역을 포함하는 제1반도체 형의기판; 상기 제2반도체 형인 제1 및 제2영역 사이에 있는 채널 영역; 상기 채널 영역 및 상기 제2반도체 형인 제1영역의 일부분상에 형성된 게이트 산화막; 및 상기 게이트 산화막 상에 형성된 플로팅 게이트를구비하며, 셀의 프로그래킹중에서 전자가 상기 플로팅 게이트로부터 상기 게이트 산화막을 통해 상기 제2반도체 형인 제1 또는 제2영역중의 하나로 흐르며, 셀의 지우기중에는 전자가 상기 제1 또는 제2영역중의 다른 하나로부터 상기 게이트 산화막을 통해 상기 플로팅 게이트로 흐르며, 상기 플로팅 게이트가 셀의 단일한 다결정실리콘 층의 일부를 이루는 것을 특징으로 하는 이이피롬 셀.A first semiconductor substrate comprising first and second regions of a second semiconductor type lying along the surface of the substrate and extending into the substrate; A channel region between the first and second regions of the second semiconductor type; A gate oxide film formed on a portion of the channel region and the first region of the second semiconductor type; And a floating gate formed on the gate oxide layer, wherein electrons flow from the floating gate to one of the first or second regions of the second semiconductor type through the gate oxide layer during programming of the cell, and during erasing of the cell. Electrons flow from the other of the first or second regions to the floating gate through the gate oxide layer, wherein the floating gate forms part of a single polysilicon layer of the cell. 제4항에 있어서, 상기 기판의 표면에 있는 영역에 형성되는 조절 게이트를 더 구비한 것을 특징으로 하는 이이피롬 셀.5. The ypyrom cell according to claim 4, further comprising a control gate formed in a region on the surface of the substrate. 제5항에 있어서, 상기 게이트 산화막이 상기 채널 영역상에 놓인 상대적으로 두꺼운 제1부분 및 제2반도체 형인 상기 제1영역의 상기 일부분상에 놓인 상대적으로 얇은 제2부분을 가지며, 상기 제1 및 제2부분을 연결하는 게이트 산화막 부분이 상기 채널 영역에 인접한 상기 제2반도체 형인 제1영역의 가장자리와 거의 정렬된 것을 특징으로 하는 이이피롬 셀.6. The semiconductor device of claim 5, wherein said gate oxide film has a relatively thick first portion overlying said channel region and a relatively thin second portion overlying said portion of said first region of a second semiconductor type. And the gate oxide layer connecting the second portion is substantially aligned with the edge of the first region of the second semiconductor type adjacent to the channel region. 제5항에 있어서, 상기 게이트 산화막이 상기 제2반도체 형인 상기 제2영역의 일부분 상에 놓인 상대적으로 얇은 제3부분을 포함하며, 상기 제1 및 제3부분을 연결하는 게이트 산화막 부분이 상기 채널 영역에 인접한 제2반도체 형인 상기 제2영역의 가장자리와 거의 정렬된 것을 특징으로 하는 이이피롬 셀.6. The gate oxide film of claim 5, wherein the gate oxide film comprises a relatively thin third portion overlying a portion of the second region of the second semiconductor type, the gate oxide portion connecting the first and third portions being the channel. And an ipyrom cell, substantially aligned with an edge of the second region, which is of a second semiconductor type adjacent to the region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950703819A 1993-03-19 1994-03-15 SINGLE POLYSILICON LAYER E²PROM CELL KR960701475A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/033,934 1993-03-19
US08/033,934 US5418390A (en) 1993-03-19 1993-03-19 Single polysilicon layer E2 PROM cell
PCT/US1994/002462 WO1994022171A1 (en) 1993-03-19 1994-03-15 Single polysilicon layer e2prom cell

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KR960701475A true KR960701475A (en) 1996-02-24

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US (1) US5418390A (en)
JP (1) JPH08507906A (en)
KR (1) KR960701475A (en)
DE (1) DE4491725T1 (en)
WO (1) WO1994022171A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3878681B2 (en) * 1995-06-15 2007-02-07 株式会社ルネサステクノロジ Nonvolatile semiconductor memory device
US5777361A (en) * 1996-06-03 1998-07-07 Motorola, Inc. Single gate nonvolatile memory cell and method for accessing the same
US5918125A (en) * 1996-09-19 1999-06-29 Macronix International Co., Ltd. Process for manufacturing a dual floating gate oxide flash memory cell
US5986931A (en) 1997-01-02 1999-11-16 Caywood; John M. Low voltage single CMOS electrically erasable read-only memory
US6201732B1 (en) * 1997-01-02 2001-03-13 John M. Caywood Low voltage single CMOS electrically erasable read-only memory
US6044018A (en) * 1998-06-17 2000-03-28 Mosel Vitelic, Inc. Single-poly flash memory cell for embedded application and related methods

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GB1392599A (en) * 1971-07-28 1975-04-30 Mullard Ltd Semiconductor memory elements
NL7500550A (en) * 1975-01-17 1976-07-20 Philips Nv SEMICONDUCTOR MEMORY DEVICE.
DE3029539A1 (en) * 1980-08-04 1982-03-11 Deutsche Itt Industries Gmbh, 7800 Freiburg NON-VOLATILE PROGRAMMABLE INTEGRATED SEMICONDUCTOR MEMORY CELL
JPS6037778A (en) * 1983-08-10 1985-02-27 Seiko Epson Corp Mos non-volatile memory cell
US4924278A (en) * 1987-06-19 1990-05-08 Advanced Micro Devices, Inc. EEPROM using a merged source and control gate
US5023680A (en) * 1988-11-10 1991-06-11 Texas Instruments Incorporated Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
US5019879A (en) * 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area

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DE4491725T1 (en) 1996-02-22
US5418390A (en) 1995-05-23
JPH08507906A (en) 1996-08-20
WO1994022171A1 (en) 1994-09-29

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