JPS6197866A - Mos type semiconductor memory device - Google Patents
Mos type semiconductor memory deviceInfo
- Publication number
- JPS6197866A JPS6197866A JP21893884A JP21893884A JPS6197866A JP S6197866 A JPS6197866 A JP S6197866A JP 21893884 A JP21893884 A JP 21893884A JP 21893884 A JP21893884 A JP 21893884A JP S6197866 A JPS6197866 A JP S6197866A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- memory device
- semiconductor memory
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は70−ティング・ゲー)MOS型半導体記憶装
置のフローティング・ゲート保護膜構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a floating gate protective film structure for a 70-gate MOS type semiconductor memory device.
従来、70−ティング・ゲー) M O−8型半導体記
憶装置における周辺保護膜はシリコン酸化膜で形成され
て成るのが通例であった。Conventionally, a peripheral protective film in a 70-Ting Gate (MO-8) type semiconductor memory device has generally been formed of a silicon oxide film.
しかし、上記従来技術によると、シリコン酸化膜中の準
位を通してフローティング・ゲートに蓄積された電子が
漏れ出し、とりわけ、フローティング・ゲートの半導体
基板側よりも測面あるいは上面への電子漏れが激しく、
そのためフローティング・ゲー)MOS型半導体記憶装
置の記憶保護時間が短かくなりたり、書き込み回数が少
なくなる等の欠点があった。However, according to the above-mentioned conventional technology, the electrons accumulated in the floating gate leak through the levels in the silicon oxide film, and in particular, electron leakage is more severe to the surface or top surface of the floating gate than to the semiconductor substrate side.
As a result, there have been disadvantages such as a shortened memory protection time and a reduced number of write operations in the floating GMOS type semiconductor memory device.
本発明は、かかる従来技術の欠点をなくシ、書き込み回
数が多くとれ、且つ記憶保持時間の長い70−ティング
・ゲー)MOS型半導体記憶装置を提供することを目的
とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to provide a 70-gate MOS semiconductor memory device which can be written many times and has a long memory retention time.
上記目的を達成するための本発明の基本的な構成は、フ
ローティング・ゲートMO3型半導体記憶装置に於て、
フローティング・ゲートの周辺にはシリコン酸化膜と、
シリコン窒化膜またはシリコン窒化物を含有せるシリコ
ン酸化膜が形成され、更にシリコン酸化膜が形成されて
成ることを特徴とする。The basic structure of the present invention for achieving the above object is that in a floating gate MO3 type semiconductor memory device,
There is a silicon oxide film around the floating gate,
It is characterized in that a silicon nitride film or a silicon oxide film containing silicon nitride is formed, and a silicon oxide film is further formed.
以下、実wAHにより本発明を詳述する。 Hereinafter, the present invention will be explained in detail using actual wAH.
第1図は、本発明の一実施例を示すフローティング・ゲ
ートMOS型牛導体記憶装置の要部の断面図である。す
なわち、81基板1の表面にはフィールド酸化膜の、ソ
ース及びドレイン拡散層5.4が形成され、更にフロー
ティング・ゲート電極5の周辺にはシリコン酸化jlf
!6tシリコン酸化醜を1000℃のアンモニア雰凹気
で処理して形成したシリコン窒化bib 7 、更にシ
リコン酸化膜8が形成されて成り、該縁結膜の一部は8
1基板1上でゲート膜として成る。FIG. 1 is a sectional view of a main part of a floating gate MOS type conductor memory device showing one embodiment of the present invention. That is, source and drain diffusion layers 5.4 of a field oxide film are formed on the surface of the 81 substrate 1, and silicon oxide film is further formed around the floating gate electrode 5.
! A silicon nitride bib 7 is formed by treating 6t silicon oxide in an ammonia atmosphere at 1000°C, and a silicon oxide film 8 is further formed, and a part of the marginal conjunctiva is formed by 8.
It is formed as a gate film on one substrate 1.
尚、シリコン窒化膜7はシリコン窒化物を含有セルシリ
コン酸化膜でありても良い。Note that the silicon nitride film 7 may be a cell silicon oxide film containing silicon nitride.
更に、本発明はドレイン側ゲート膜の一部を薄くしたF
XIIiPROMにも適用できることは云うまでもない
。Furthermore, the present invention has a structure in which the gate film on the drain side is partially thinned
Needless to say, it can also be applied to XIIiPROM.
本発明の如く、フローティング・ゲート周辺をシリコン
酸化膜・シリコン窒化膜・シリコン酸化膜の3層構造膜
で保護することに上り緻細膜内準位と、界面準位を少な
くすることができ、7四−ティング・ゲー)MO5IJ
半導体記憶装置の記憶保持時間の延長及び書き込み回数
の増大を計ることができる効果がある。As in the present invention, by protecting the periphery of the floating gate with a three-layer structure film of silicon oxide film, silicon nitride film, and silicon oxide film, it is possible to reduce the level in the fine film and the level at the interface. 74-ting game) MO5IJ
This has the effect of extending the memory retention time of the semiconductor memory device and increasing the number of writes.
第1図は本発明の一実施例を示すフルーティング・ゲー
)MOS娶半導体記憶装置の要部の断面図である。
1・・・・・・81基板
2・・・・・・フィールド酸化膜
5.4・・・・・・拡散層
5・・・・・・フ胃−ティング・ゲート電極6.8・・
・・・・シリコン酸化膜
7・・・・・・シリコン窒化膜FIG. 1 is a sectional view of a main part of a fluting/MOS semiconductor memory device showing one embodiment of the present invention. 1...81 Substrate 2...Field oxide film 5.4...Diffusion layer 5...Funging gate electrode 6.8...
...Silicon oxide film 7...Silicon nitride film
Claims (1)
、シリコン窒化膜またはシリコン窒化物を含有せるシリ
コン酸化膜が形成され、更にシリコン酸化膜が形成され
て成る事を特徴とするMOS型半導体記憶装置。A MOS type semiconductor memory device characterized in that a silicon oxide film, a silicon nitride film or a silicon oxide film containing silicon nitride are formed around a floating gate, and a silicon oxide film is further formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21893884A JPS6197866A (en) | 1984-10-18 | 1984-10-18 | Mos type semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21893884A JPS6197866A (en) | 1984-10-18 | 1984-10-18 | Mos type semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6197866A true JPS6197866A (en) | 1986-05-16 |
Family
ID=16727677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21893884A Pending JPS6197866A (en) | 1984-10-18 | 1984-10-18 | Mos type semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6197866A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6455868A (en) * | 1987-08-27 | 1989-03-02 | Toshiba Corp | Rewritable read only memory |
US4881108A (en) * | 1987-03-26 | 1989-11-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
US5319230A (en) * | 1991-09-11 | 1994-06-07 | Rohm Co., Ltd. | Non-volatile storage device |
US5652449A (en) * | 1988-02-13 | 1997-07-29 | Kabushiki Kaisha Toshiba | Semiconductor device with an insulating film separating conductive layers and method of maufacturing semiconductor device |
US5712208A (en) * | 1994-06-09 | 1998-01-27 | Motorola, Inc. | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants |
US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
-
1984
- 1984-10-18 JP JP21893884A patent/JPS6197866A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4881108A (en) * | 1987-03-26 | 1989-11-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
JPS6455868A (en) * | 1987-08-27 | 1989-03-02 | Toshiba Corp | Rewritable read only memory |
US5652449A (en) * | 1988-02-13 | 1997-07-29 | Kabushiki Kaisha Toshiba | Semiconductor device with an insulating film separating conductive layers and method of maufacturing semiconductor device |
US5319230A (en) * | 1991-09-11 | 1994-06-07 | Rohm Co., Ltd. | Non-volatile storage device |
US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
US5712208A (en) * | 1994-06-09 | 1998-01-27 | Motorola, Inc. | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants |
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