JPH011276A - semiconductor storage device - Google Patents
semiconductor storage deviceInfo
- Publication number
- JPH011276A JPH011276A JP62-157293A JP15729387A JPH011276A JP H011276 A JPH011276 A JP H011276A JP 15729387 A JP15729387 A JP 15729387A JP H011276 A JPH011276 A JP H011276A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- oxide film
- silicon
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- LOPFACFYGZXPRZ-UHFFFAOYSA-N [Si].[As] Chemical compound [Si].[As] LOPFACFYGZXPRZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、紫外線の照射により記憶した情報を消去可
能な半導体記憶装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory device capable of erasing stored information by irradiation with ultraviolet rays.
第２図は、従来の半導体記憶装置を示す断面図であり、
図において、シリコン基板（１〕上に、シリコン酸化膜
（２）を介して、多結晶シリコンから成るフロー子ィン
グゲート（３）を形成し、さらに、同様に、シリコン酸
化膜（２）を介してコントロールゲート（４）を形成し
、全体をシリコン酸化膜（２）で覆っている。FIG. 2 is a cross-sectional view showing a conventional semiconductor memory device,
In the figure, a flow child gate (3) made of polycrystalline silicon is formed on a silicon substrate (1) with a silicon oxide film (2) interposed therebetween; A control gate (4) is formed thereon, and the entire structure is covered with a silicon oxide film (2).
次に、ドレインとソースとなる不純物拡散層（５）を形
成し、ＣＶＤ法等により、絶縁膵（６）を形成し、アル
ミ蒸着とフォトエツチングにより金Ｆｆ４ 配線（７）
を形成する。そして、パッケージとの接続部を除いてＣ
ＶＤ法により形成したシリコン酸化膜（８）で守に示す
様な半導体装置は、通常サーデイツプと呼ばれる、表面
に透光性の窓のついたパッケージに封入されているが、
この窓から強いエネルギーを持った紫外線（通常波長が
２５３７Ａでエネルギは４．３ ｅＶ ）がメモリセル
部に照射されると、シリコン酸ｆヒ膜（８）を透過しフ
ローティングゲート中の電子が励起され、酸化膜のエネ
ルギー障壁を越えてコントロールゲートやシリコン基板
に散失する。Next, an impurity diffusion layer (5) that will become the drain and source is formed, an insulating layer (6) is formed by CVD, etc., and a gold Ff4 wiring (7) is formed by aluminum evaporation and photoetching.
form. Then, except for the connection part with the package, C
Semiconductor devices like the one shown in Mamoru, which are made of a silicon oxide film (8) formed by the VD method, are usually enclosed in a package with a transparent window on the surface called a cerdip.
When the memory cell area is irradiated with ultraviolet rays with strong energy (normal wavelength is 2537A and energy is 4.3 eV) from this window, it passes through the silicon arsenic film (8) and excites the electrons in the floating gate. It crosses the energy barrier of the oxide film and is dissipated into the control gate and silicon substrate.
この様にフローティングゲート中に電子のない状態が情
報が消去された状態である。A state in which there are no electrons in the floating gate is a state in which information is erased.
従来の半導体記憶装置は以上の様に、通常高価な消去窓
付パッケージに封入されているが、この替わりにＯＴ
Ｐ （Ｏｎｅ Ｔｉｒｎｅ ＰＲＯＭ） と呼ばれる
安価ナプラスチックパッケージに封入する製品の場合、
チップの保護膜として用いられるシリコン酸化膜では耐
湿性、強度等が弱く、半導体記憶装置の信頼性上問題が
あった。As mentioned above, conventional semiconductor memory devices are usually enclosed in expensive packages with erasure windows, but instead of this, OT
In the case of a product sealed in an inexpensive plastic package called P (One Tierne PROM),
A silicon oxide film used as a protective film for a chip has poor moisture resistance, strength, etc., and this poses problems in terms of reliability of semiconductor memory devices.
この発明は上記の様な問題点を解消するためになされた
もので、耐湿性に優れ、強度もあり、かつ、記憶内容消
去のための紫外線を十分透過させる様な、保護膜を備え
た半導体記憶装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is a semiconductor with a protective film that has excellent moisture resistance and strength, and that allows sufficient penetration of ultraviolet rays for erasing memory contents. The purpose is to obtain a storage device.
この発明に係る半導体記憶装置は、保護膜として、シリ
コン酸化膜とシリコン窒化膜の多層膜としたものである
。The semiconductor memory device according to the present invention uses a multilayer film of a silicon oxide film and a silicon nitride film as a protective film.
この発明における保護膜はシリコン酸化膜と耐湿斗、強
度にすぐれたシリコン窒化膜との多層膜としたため、紫
外線透過特性をそこなうことなく、耐湿性及び強度が向
上する。Since the protective film in this invention is a multilayer film of a silicon oxide film, a moisture-resistant film, and a silicon nitride film with excellent strength, moisture resistance and strength are improved without impairing ultraviolet transmission characteristics.
以下、この発明の一実施例を図について説明する。第１
図において、シリコン基板（１）上に、シリコン酸化膜
（２）を介して多結晶シリコンから成るフローティング
ゲート（４）を形成し、さらに、同様に、シリコン酸化
膜（２１を介して、コントロールゲート（４）を形成し
た後、シリコン酸化膜（２）で覆う。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, a floating gate (4) made of polycrystalline silicon is formed on a silicon substrate (1) through a silicon oxide film (2), and a control gate (4) is similarly formed through a silicon oxide film (21). After forming (4), it is covered with a silicon oxide film (2).
次に、ドレインとソースになる不純物拡散層（５）を形
成し、ＣＶＤ法等で絶縁膜（６）を形成し、アルミ蒸着
とフォトエツチング技術を駆使して、金に配線（７）を
形成する。さらに、保護膜としてＣＶＤ法でシリコン酸
化膜（８）をデボした後、シリコン窒化膜（９）を形成
し、パッド部分を開孔する。Next, an impurity diffusion layer (5) that will become the drain and source is formed, an insulating film (6) is formed by CVD, etc., and a wiring (7) is formed on the gold using aluminum vapor deposition and photoetching technology. do. Furthermore, after a silicon oxide film (8) is deposited as a protective film by CVD, a silicon nitride film (9) is formed, and a hole is opened at the pad portion.
次に、保ｔｔ膜として、シリコン酸化１ｉ （８）とシ
リコン窒化膜（９）の多層構造とした場合の効果につい
て１説明する。Next, the effect of using a multilayer structure of silicon oxide 1i (8) and silicon nitride film (9) as the protective tt film will be explained.
従来の保護膜であるシリコン酸化膜に代わり、シリコン
窒化膜を用いることにより、耐湿性及強度は向上される
が、通常の屈折率がｎ −２，０程度のシリコン窒化膜
は、記憶内容の消去に用いる波長がλ−２５３７Ａの紫
外線をほとんど透過しないため、記憶内容を消去できな
かった。Moisture resistance and strength are improved by using a silicon nitride film in place of the conventional silicon oxide film, but the silicon nitride film, which has a normal refractive index of about n-2.0, cannot hold the memory contents. The stored contents could not be erased because almost no ultraviolet light having a wavelength of λ-2537A used for erasing was transmitted.
シリコン窒化膜の形成時の条件を変えることで、屈折率
をｎ −１，９程度まで低下させ、かつ膜厚を薄くする
ことで、紫外線透過率を１０％ 以上に高めることがで
きることがわかっている。しかし、１嘆厚を薄くすると
、強度、耐湿性の向上が期待できなくなることから、紫
外線透過性の良いシリコン酸化膜と、シリコン窒化膜と
を組み合わせることにより、透過性を維持しながら、強
度、耐湿性を向上することができる。It has been found that by changing the conditions during the formation of the silicon nitride film, the refractive index can be lowered to about n -1.9, and by reducing the film thickness, it is possible to increase the ultraviolet transmittance to more than 10%. There is. However, if the thickness is reduced by one inch, it is no longer possible to expect improvements in strength and moisture resistance, so by combining a silicon oxide film with good ultraviolet transmittance and a silicon nitride film, the strength and moisture resistance can be improved while maintaining transparency. Moisture resistance can be improved.
以上の様に、この発明によれば、記憶情報を消去可能な
半導体装置の保護膜を、シリコン酸化膜とシリコン窒化
膜の２層溝造としたので、紫外線透過能力を損なうこと
がなく、この半導体装着をプラスチックパッケージに封
入した際の：耐湿性及び・強度が改善されるという効用
がある。As described above, according to the present invention, since the protective film of a semiconductor device in which stored information can be erased is made of a two-layer groove structure of a silicon oxide film and a silicon nitride film, the ultraviolet transmitting ability is not impaired. It has the effect of improving moisture resistance and strength when semiconductor mounting is encapsulated in a plastic package.
置を示す断面図、第２図は、従来の半導体装置ぢ示す断
面図である。FIG. 2 is a sectional view showing a conventional semiconductor device.
図において、（１）はシリコン基板、（２）はシリコン
酸化膜、（３）はフローティングゲート、（４）はコン
トロールゲート、（５）は不純物拡散層、（６）は絶縁
膜、（７）は金属配線、（８）はシリコン酸化膜、（９
）はシリコン窒化、ｖｊ：である。In the figure, (1) is a silicon substrate, (2) is a silicon oxide film, (3) is a floating gate, (4) is a control gate, (5) is an impurity diffusion layer, (6) is an insulating film, (7) is a is metal wiring, (8) is silicon oxide film, (9
) is silicon nitride, vj:.
なお、図中、同一符号は同一、又は相当部分を示す。In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
憶装置において、 チップの保護膜としてシリコン酸化膜とシリコン窒化膜
との多層構造膜を用いるようにしたことを特徴とする半
導体記憶装置。(1) A semiconductor memory device whose memory contents can be erased by ultraviolet irradiation, characterized in that a multilayer structure film of a silicon oxide film and a silicon nitride film is used as a chip protection film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-157293A JPH011276A (en) | 1987-06-23 | semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62-157293A JPH011276A (en) | 1987-06-23 | semiconductor storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS641276A JPS641276A (en) | 1989-01-05 |
| JPH011276A true JPH011276A (en) | 1989-01-05 |
Family
ID=
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